Search results for "Kia Bazargan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Peng Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja	The synthesis of linear Finite State Machine-based Stochastic Computational Elements.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Weikang Qian, Xin Li, Marc D. Riedel, Kia Bazargan, David J. Lilja	An Architecture for Fault-Tolerant Computation with Stochastic Logic.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Hossein Omidian Savarbaghi, Kia Bazargan	FPGA placement by graph isomorphism (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Kia Bazargan	Improvements on Efficiency and Efficacy of SPFD-Based Rewiring for LUT-Based Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Kia Bazargan	A fast SPFD-based rewiring technique.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan	Fast and Accurate Statistical Criticality Computation Under Process Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Satish Sivaswamy, Kia Bazargan, Marc D. Riedel	Estimation and optimization of reliability of noisy digital circuits.	ISQED	2009	DBLP DOI BibTeX RDF
1	Xin Li, Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja	A reconfigurable stochastic architecture for highly reliable computing.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	stochastic logic, reconfigurable architecture, reliable computing
1	Hamid Safizadeh, Mohammad Tahghighi, Ehsan K. Ardestani, Gholamhossein Tavasoli, Kia Bazargan	Using randomization to cope with circuit uncertainty.	DATE	2009	DBLP BibTeX RDF
1	Seyyed Ahmad Razavi, Morteza Saheb Zamani, Kia Bazargan	A tileable switch module architecture for homogeneous 3D FPGAs.	3DIC	2009	DBLP DOI BibTeX RDF
1	Weikang Qian, Marc D. Riedel, Kia Bazargan, David J. Lilja	The synthesis of combinational logic to generate probabilities.	ICCAD	2009	DBLP BibTeX RDF
1	Satish Sivaswamy, Kia Bazargan	Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs.	TRETS	2008	DBLP DOI BibTeX RDF	skew assignment, routing, Statistical timing analysis
1	Pongstorn Maidee, Nagib Hakim, Kia Bazargan	FPGA family composition and effects of specialized blocks.	FPL	2008	DBLP DOI BibTeX RDF
1	Hushrav Mogal, Kia Bazargan	Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Kia Bazargan, André DeHon	Guest Editorial.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Kia Bazargan	A generalized and unified SPFD-based rewiring technique.	FPL	2007	DBLP DOI BibTeX RDF
1	Satish Sivaswamy, Kia Bazargan	Statistical Generic And Chip-Specific Skew Assignment for Improving Timing Yield of FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
1	Satish Sivaswamy, Kia Bazargan	Variation-aware routing for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	statistical timing analysis, FPGA routing
1	Hushrav Mogal, Kia Bazargan	Microarchitecture floorplanning for sub-threshold leakage reduction.	DATE	2007	DBLP DOI BibTeX RDF
1	Hushrav Mogal, Haifeng Qian, Sachin S. Sapatnekar, Kia Bazargan	Clustering based pruning for statistical criticality computation under process variations.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Kia Bazargan	Non-contiguous linear placement for reconfigurable fabrics.	IJES	2006	DBLP DOI BibTeX RDF
1	Gang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh	Statistical Analysis and Design of HARP FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Hushrav Mogal, Kia Bazargan	Three-dimensional place and route for FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Kia Bazargan	Defect-Tolerant FPGA Architecture Exploration.	FPL	2006	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Timing-driven partitioning-based placement for island style FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan	A Novel Memory Structure for Embedded Systems: Flexible Sequential and Random Access Memory.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	sequential access buffer, media benchmark, flexible sequential and random access memory, on-chip memory
1	Cristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar	Placement and Routing in 3D Integrated Circuits.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	VLSI, Placement and routing
1	Cristinel Ababei, Hushrav Mogal, Kia Bazargan	Three-dimensional place and route for FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Satish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh	HARP: hard-wired routing pattern FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Hushrav Mogal, Kia Bazargan	3D FPGAs: placement, routing, and architecture evaluation (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
1	John Lach, Kia Bazargan	Editorial: Special issue on dynamically adaptable embedded systems.	ACM Trans. Embedded Comput. Syst.	2004	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Pongstorn Maidee, Kia Bazargan	Exploring Potential Benefits of 3D FPGA Integration.	FPL	2004	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Kia Bazargan	Non-Contiguous Linear Placement for Reconfigurable Fabrics.	IPDPS	2004	DBLP DOI BibTeX RDF
1	Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan	Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
1	Karthikeyan Bhasyam, Kia Bazargan	HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming.	DSD	2003	DBLP DOI BibTeX RDF
1	Pongstorn Maidee, Cristinel Ababei, Kia Bazargan	Fast timing-driven partitioning-based placement for island style FPGAs.	DAC	2003	DBLP DOI BibTeX RDF	FPGA placement, partitioning based placement, FPGAs, timing-driven placement
1	Vamsi Krishna Marreddy, Sharareh Noorbaloochi, Kia Bazargan	Linear Placement for Static / Dynamic Reconfiguration in JBits. (PDF / PS)	FCCM	2003	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Kia Bazargan	Timing Minimization by Statistical Timing hMetis-based Partitioning.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Wonjoon Choi, Kia Bazargan	Hierarchical Global Floorplacement Using Simulated Annealing and Network Flow Area Migration.	DATE	2003	DBLP DOI BibTeX RDF	floorplacement, global placement, area migration, Design, Algorithms, simulated annealing, Management, Floorplanning, network flow, hierarchical, Placement and routing
1	Cristinel Ababei, Kia Bazargan	Placement Method Targeting Predictability Robustness and Performance.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Wonjoon Choi, Kia Bazargan	Incremental Placement for Timing Optimization.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Jinghuan Chen, Jaekyun Moon, Kia Bazargan	A reconfigurable FPGA-based readback signal generator for hard-drive read channel simulator.	DAC	2002	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Kia Bazargan	Statistical Timing Driven Partitioning for VLSI Circuits.	DATE	2002	DBLP DOI BibTeX RDF
1	Cristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis	Multi-objective circuit partitioning for cutsize and path-based delay minimization.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Abhishek Ranjan, Kia Bazargan, S. Ogrenci, Majid Sarrafzadeh	Fast floorplanning for effective prediction and construction.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh	Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures.	DAC	2001	DBLP DOI BibTeX RDF
1	Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh	3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems.	Design Autom. for Emb. Sys.	2000	DBLP DOI BibTeX RDF
1	Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh	Fast Template Placement for Reconfigurable Computing Systems.	IEEE Design & Test of Computers	2000	DBLP DOI BibTeX RDF
1	Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh	Fast and accurate estimation of floorplans in logic/high-level synthesis.	ACM Great Lakes Symposium on VLSI	2000	DBLP DOI BibTeX RDF
1	Kia Bazargan, Ryan Kastner, Seda Ogrenci, Majid Sarrafzadeh	A C to Hardware/Software Compiler.	FCCM	2000	DBLP DOI BibTeX RDF
1	Abhishek Ranjan, Kia Bazargan, Majid Sarrafzadeh	Fast Hierarchical Floorplanning with Congestion and Timing Control. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Kia Bazargan, Samjung Kim, Majid Sarrafzadeh	Nostradamus: a floorplanner of uncertain designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh	3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	3-D floorplanning, Reconfigurable computing, floorplanning
1	Kia Bazargan, Samjung Kim, Majid Sarrafzadeh	Nostradamus: a floorplanner of uncertain design.	ISPD	1998	DBLP DOI BibTeX RDF

Publications of "Kia Bazargan" ( http://dblp.L3S.de/Authors/Kia_Bazargan )