Search results for "Kimiyoshi Usami"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura	Efficient leakage power saving by sleep depth controlling for Multi-mode Power Gating.	ISQED	2012	DBLP DOI BibTeX RDF
1	Seidai Takeda, Shinobu Miwa, Kimiyoshi Usami, Hiroshi Nakamura	Stepwise sleep depth control for run-time leakage power saving.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	A multi-Vdd dynamic variable-pipeline on-chip router for CMPs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Seidai Takeda, Kyundong Kim, Hiroshi Nakamura, Kimiyoshi Usami	Sleep Transistor Sizing Method Using Accurate Delay Estimation Considering Input Vector Pattern and Non-linear Current Model.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo	Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Yuya Goto, Kensaku Matsunaga, Satoshi Koyama, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura	On-chip detection methodology for break-even time of power gated function units.	ISLPED	2011	DBLP BibTeX RDF
1	Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo	Cool Mega-Array: A highly energy efficient reconfigurable accelerator.	FPT	2011	DBLP DOI BibTeX RDF
1	Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo	Geyser-2: The second prototype CPU with fine-grained run-time power gating.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Tatsuya Yamamoto, Kazuei Hironaka, Yuki Hayakawa, Masayuki Kimura, Hideharu Amano, Kimiyoshi Usami	Dynamic VDD Switching Technique and Mapping Optimization in Dynamically Reconfigurable Processor for Efficient Energy Reduction.	ARC	2011	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	Adaptive power gating for function units in a microprocessor.	ISQED	2010	DBLP DOI BibTeX RDF
1	Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano	Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs.	NOCS	2010	DBLP DOI BibTeX RDF	low power, Network-on-Chip, router, power gating
1	Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo	Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Lei Zhao, Hui Xu, Naomi Seki, Yoshiki Saito, Yohei Hasegawa, Kimiyoshi Usami, Hideharu Amano	Cache Controller Design on Ultra Low Leakage Embedded Processors.	ARCS	2009	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura	Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Jerry Frenkil, Ken Choi, Kimiyoshi Usami	Power Gating for Ultra-low Leakage: Physics, Design, and Analysis.	DATE	2008	DBLP DOI BibTeX RDF
1	Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura	A fine-grain dynamic sleep control scheme in MIPS R3000.	ICCD	2008	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami	Overview on Low Power SoC Design Technology.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Naoaki Ohkubo, Kimiyoshi Usami	Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Naoaki Ohkubo, Kimiyoshi Usami	Delay modeling and static timing analysis for MTCMOS circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF	interpolation., selective-MT, delay, leakage power, static timing analysis, MTCMOS
1	Kimiyoshi Usami, Naoaki Ohkubo	A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals.	ICCD	2006	DBLP BibTeX RDF
1	Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak	Code Coverage-Based Power Estimation Techniques for Microprocessors.	Journal of Circuits, Systems, and Computers	2002	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa	Automated selective multi-threshold design for ultra-low standby applications.	ISLPED	2002	DBLP DOI BibTeX RDF	standby leakage current, automated design, multi-threshold
1	Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak	Function-level power estimation methodology for microprocessors.	DAC	2000	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Mutsunori Igarashi	Low-power design methodology and applications utilizing dual supply voltages.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Masafumi Takahashi, Mototsugu Hamada, Hideho Arakida, Toshihiro Terazawa, Tadahiro Kuroda	Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
1	Takeshi Kitahara, Fumihiro Minami, Toshiaki Ueda, Kimiyoshi Usami, Seiichi Nishio, Masami Murakata, Takashi Mitsuhashi	A Clock-Gating Method for Low-Power LSI Design.	ASP-DAC	1998	DBLP BibTeX RDF
1	Mutsunori Igarashi, Kimiyoshi Usami, Kazutaka Nogami, Fumihiro Minami, Yukio Kawasaki, Takahiro Aoki, Midori Takano, Chiharo Mizuno, Takashi Ishikawa, Masahiro Kanazawa, Shinji Sonoda, Makoto Ichida, Naoyuki Hatanaka	A low-power design method using multiple supply voltages.	ISLPED	1997	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Mark Horowitz	Clustered voltage scaling technique for low-power design.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Nobu Matsumoto, Yoko Watanabe, Kimiyoshi Usami, Yukio Sugeno, Hiroshi Hatada, Shojiro Mori	Datapath Generator Based on Gate-Level Symbolic Layout.	DAC	1990	DBLP DOI BibTeX RDF

Publications of "Kimiyoshi Usami" ( http://dblp.L3S.de/Authors/Kimiyoshi_Usami )