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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6 occurrences of 5 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Taecheol Oh, Kiyeon Lee, Sangyeun Cho |
An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing.  |
MASCOTS  |
2011 |
DBLP DOI BibTeX RDF |
simulation, performance modeling, Chip multiprocessor (CMP), resource sharing |
| 1 | Kiyeon Lee, Sangyeun Cho |
In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces. |
MASCOTS |
2011 |
DBLP DOI BibTeX RDF |
Superscalar out-of-order processor, performance modeling, trace-driven simulation |
| 1 | Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, Sangyeun Cho |
Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach. |
Softw., Pract. Exper. |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Taecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho |
An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Kiyeon Lee, Shayne Evans, Sangyeun Cho |
Accurately approximating superscalar processor performance from traces. |
ISPASS |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Sangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, Michael Moeng |
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation. |
ICPP |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Sangyeun Cho, Lei Jin, Kiyeon Lee |
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems. |
RTCSA |
2007 |
DBLP DOI BibTeX RDF |
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