| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi |
Active Memory Processor for Network-on-Chip-Based Architecture.  |
IEEE Trans. Computers  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinho Lee, Kiyoung Choi |
Memory-aware mapping and scheduling of tasks and communications on many-core SoC. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyuseung Han, Seongsik Park, Kiyoung Choi |
State-based full predication for low power coarse-grained reconfigurable architecture. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Ganghee Lee, Kiyoung Choi, Nikil D. Dutt |
Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jong Kyung Paek, Jong-eun Lee, Kiyoung Choi |
CRM: Configurable Range Memory for Fast Reconfigurable Computing. |
IPDPS Workshops |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Junwhan Ahn, Imyong Lee, Kiyoung Choi |
A polynomial-time custom instruction identification algorithm based on dynamic programming. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunjik Song, Kiyoung Choi |
Simulated annealing-based diffusive load balancing on many-core SoC. |
ICAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Seokhyun Lee, Kiyoung Choi |
High-level synthesis with distributed controller for fast timing closure. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Junwhan Ahn, Kiyoung Choi |
An efficient algorithm for isomorphism-aware custom instruction identification for extensible processors. |
CODES+ISSS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganghee Lee, Yongjin Ahn, Seokhyun Lee, Jeongki Son, Kiwook Yoon, Kiyoung Choi |
Communication architecture design for reconfigurable multimedia SoC platform. |
Design Autom. for Emb. Sys. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jong Kyung Paek, Kiyoung Choi, Jong-eun Lee |
Binary acceleration using coarse-grained reconfigurable architecture. |
SIGARCH Computer Architecture News |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoonjin Kim, Rabi N. Mahapatra, Kiyoung Choi |
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyuseung Han, Jong Kyung Paek, Kiyoung Choi |
Acceleration of control flow on CGRA using advanced predicated execution. |
FPT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganghee Lee, Kyungwook Chang, Kiyoung Choi |
Automatic mapping of control-intensive kernels onto coarse-grained reconfigurable array architecture with speculative execution. |
IPDPS Workshops |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyungwook Chang, Kiyoung Choi |
Memory-Centric Communication Architecture for Reconfigurable Computing. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil D. Dutt |
Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. |
ARC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, Kiyoung Choi |
Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi |
Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi |
Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
System-on-Chip, Network-on-Chip, computer architecture |
| 1 | Youngchul Cho, Kiyoung Choi |
Code decomposition and recomposition for enhancing embedded software performance. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Manhwee Jo, Ganghee Lee, Kyungwook Chang, Kyuseung Han, Kiyoung Choi, Hoonmo Yang, Kiwook Yoon |
Coarse-grained reconfigurable architecture for multiple application domains: a case study. |
ICHIT |
2009 |
DBLP DOI BibTeX RDF |
system design, coarse-grained reconfigurable architecture |
| 1 | Soonhoi Ha, Kiyoung Choi, Taewhan Kim, Krisztián Flautner, Sang Lyul Min, Wang Yi |
Introduction to embedded systems week 2006 special issue. |
ACM Trans. Embedded Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongjin Ahn, Keesung Han, Ganghee Lee, Hyunjik Song, Jun-hee Yoo, Kiyoung Choi, Xingguang Feng |
SoCDAL: System-on-chip design AcceLerator. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
application-to-architecture mapping, static hardware/software estimation, simulation, scheduling, specification, design-space exploration, worst-case execution time, Codesign, transaction-level model, synchronous dataflow, multiprocessor system-on-chip, process networks |
| 1 | Jong-eun Lee, Kiyoung Choi, Nikil Dutt |
Evaluating memory architectures for media applications on Coarse-grained Reconfigurable Architectures. |
IJES |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | V. K. Prasad Arava, Manhwee Jo, HyoukJoong Lee, Kiyoung Choi |
A Generic Design for Encoding and Decoding Variable Length Codes in Multi-codec Video Processing Engines. |
ISVLSI |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongwook Lee, Sungjoo Yoo, Kiyoung Choi |
Entry control in network-on-chip for memory power reduction. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngchul Cho, Nacer-Eddine Zergainoh, Sungjoo Yoo, Ahmed Amine Jerraya, Kiyoung Choi |
Scheduling with accurate communication delay model and scheduler implementation for multiprocessor system-on-chip. |
Design Autom. for Emb. Sys. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinyong Jung, Sungjoo Yoo, Kiyoung Choi |
Fast cycle-approximate MPSoC simulation based on synchronization time-point prediction. |
Design Autom. for Emb. Sys. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Instruction set synthesis with efficient instruction encoding for configurable processors. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding |
| 1 | Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi |
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Ganghee Lee, Seokhyun Lee, Yongjin Ahn, Kiyoung Choi |
Automatic Bus Matrix Synthesis based on Hardware Interface Selection for Fast Communication Design Space Exploration. |
ICSAMOS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngchul Cho, Nacer-Eddine Zergainoh, Kiyoung Choi, Ahmed Amine Jerraya |
Low Runtime-Overhead Software Synthesis for Communicating Concurrent Processes. |
IEEE International Workshop on Rapid System Prototyping |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Imyong Lee, Dongwook Lee, Kiyoung Choi |
Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation. |
ASAP |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi |
Communication Architecture Synthesis of Cascaded Bus Matrix. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
AMBA3 AXI, cascaded bus matrix, on-chip communication architecture, bus topology, encoding method, traffic group encoding, simulated annealing, design space exploration |
| 1 | Youngchul Cho, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya, Kiyoung Choi |
Buffer Size Reduction through Control-Flow Decomposition. |
RTCSA |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Manhwee Jo, V. K. Prasad Arava, Hoonmo Yang, Kiyoung Choi |
Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture. |
SoCC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Soonhoi Ha, Kiyoung Choi, Nikil D. Dutt, Jürgen Teich (eds.) |
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007 |
CODES+ISSS |
2007 |
DBLP BibTeX RDF |
|
| 1 | Yoonjin Kim, Ilhyun Park, Kiyoung Choi, Yunheung Paek |
Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
coarse-grained reconfigurable architecture (CGRA), context pipelining, temporal mapping, low power, system-on-chip (SoC), loop pipelining, configuration cache, spatial mapping |
| 1 | Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi |
Worst case execution time analysis for synthesized hardware. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Minwook Ahn, Jonghee W. Yoon, Yunheung Paek, Yoonjin Kim, Mary Kiemb, Kiyoung Choi |
A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Reinaldo A. Bergamaschi, Kiyoung Choi (eds.) |
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006 |
CODES+ISSS |
2006 |
DBLP BibTeX RDF |
|
| 1 | Daehong Kim, Dongwan Shin, Kiyoung Choi |
Pipelining with common operands for power-efficient linear systems. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngchul Cho, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya |
Scheduler implementation in MP SoC design. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yoonjin Kim, Mary Kiemb, Chulsoo Park, Jinyong Jung, Kiyoung Choi |
Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture for Domain-Specific Optimization. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy (eds.) |
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004 |
ISLPED |
2004 |
DBLP BibTeX RDF |
|
| 1 | Whee Kuk Kim, Kiyoung Choi, Byung-Ju Yi |
A Mobility Analysis Method of Closed-chain Mechanisms with Over-constraints and Non-holonomic Constraints. |
ICRA |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Mary Kiemb, Kiyoung Choi |
Memory and architecture exploration with thread shifting for multithreaded processors in embedded systems. |
CASES |
2004 |
DBLP DOI BibTeX RDF |
embedded systems, design space exploration, simultaneous multithreading, SMT |
| 1 | Mary Kiemb, Kiyoung Choi |
Application-specific configuration of multithreaded processor architecture for embedded applications. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, Soo-Ik Chae |
An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design. |
Design Autom. for Emb. Sys. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikil D. Dutt, Kiyoung Choi |
Configurable Processors for Embedded Computing. |
IEEE Computer |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Compilation Approach for Coarse-Grained Reconfigurable Architectures. |
IEEE Design & Test of Computers |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Energy-efficient instruction set synthesis for application-specific processors. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
low power, customization, application-specific instruction set processor (ASIP), instruction encoding, energy-delay product |
| 1 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung Choi, Nacer-Eddine Zergainoh |
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt |
An algorithm for mapping loops onto coarse-grained reconfigurable architectures. |
LCTES |
2003 |
DBLP DOI BibTeX RDF |
ALU array, memory bandwidth utilization, coarse-grained reconfigurable architecture, mapping algorithm |
| 1 | Sunghyun Lee, Kiyoung Choi, Sungjoo Yoo |
An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
variable supply voltage, low power, finite state machine, dynamic voltage scaling, formal model, synchronous dataflow |
| 1 | Jong-eun Lee, Kiyoung Choi, Nikil Dutt |
Efficient instruction encoding for automatic instruction set design of configurable ASIPs. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sunghyun Lee, Sungjoo Yoo, Kiyoung Choi |
Reconfigurable SoC design with hierarchical FSM and synchronous dataflow model. |
CODES |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanghun Park, Kiyoung Choi |
Performance-driven high-level synthesis with bit-level chaining andclock selection. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi |
Partial bus-invert coding for power optimization of application-specific systems. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngsoo Shin, Kiyoung Choi, Young-Hoon Chang |
Narrow bus encoding for low-power DSP systems. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Daehong Kim, Dongwan Shin, Kiyoung Choi |
Low power pipelining of linear systems: a common operand centric approach. |
ISLPED |
2001 |
DBLP DOI BibTeX RDF |
common operand, operand sharing, low power, pipelining |
| 1 | Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi |
High-level synthesis under multi-cycle interconnect delay. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinyong Jung, Sungjoo Yoo, Kiyoung Choi |
Performance improvement of multi-processor systems cosimulation based on SW analysis. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Daehong Kim, Jinyong Jung, Sunghyun Lee, Jinhwan Jeon, Kiyoung Choi |
Behavior-to-Placed RTL Synthesis with Performance-Driven Placement. |
ICCAD |
2001 |
DBLP BibTeX RDF |
|
| 1 | Sungtaek Lim, Jihong Kim, Kiyoung Choi |
Scheduling-based code size reduction in processors with indirect addressing mode. |
CODES |
2001 |
DBLP DOI BibTeX RDF |
indirect addressing mode, code generation, code size reduction, storage assignment |
| 1 | Kyoungseok Rha, Kiyoung Choi |
Area-efficient buffer binding based on a novel two-port FIFO structure. |
CODES |
2001 |
DBLP DOI BibTeX RDF |
buffer binding, buffer sharing, scheduling, SDF |
| 1 | Sungjoo Yoo, Kiyoung Choi |
Optimizing Timed Cosimulation by Hybrid Synchronization. |
Design Autom. for Emb. Sys. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungjoo Yoo, Kiyoung Choi, Dong Sam Ha |
Performance improvement of geographically distributed cosimulation by hierarchically grouped messages. |
IEEE Trans. VLSI Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Jae-Hee Won, Kiyoung Choi |
Low power self-timed Radix-2 division (poster session). |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
RSD, radix-2 division, low power, self-timed |
| 1 | Junghwan Choi, Jinhwan Jeon, Kiyoung Choi |
Power minimization of functional units partially guarded computation. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
partially guarded computation, low power |
| 1 | Youngsoo Shin, Daehong Kim, Kiyoung Choi |
Schedulability-driven performance analysis of multiple mode embedded real-time systems. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngsoo Shin, Kiyoung Choi |
Narrow bus encoding for low power systems. |
ASP-DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Byungil Jeong, Sungjoo Yoo, Sunghyun Lee, Kiyoung Choi |
Hardware-software cosynthesis for run-time incrementally reconfigurable FPGAs. |
ASP-DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi |
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai |
Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Sungjoo Yoo, Kyoungseok Rha, Youngchul Cho, Jinyong Jung, Kiyoung Choi |
Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model. |
CODES |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngsoo Shin, Kiyoung Choi |
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanghun Park, Kiyoung Choi |
Performance-Driven Scheduling with Bit-Level Chaining. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Byungil Jeong, Sungjoo Yoo, Kiyoung Choi |
Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable FPGAs in Embedded Systems Design. |
FPGA |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungjoo Yoo, Kiyoung Choi |
Optimizing geographically distributed timed cosimulation by hierarchically grouped messages. |
CODES |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Kiyoung Choi |
An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping. |
Design Autom. for Emb. Sys. |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi |
Partial bus-invert coding for power optimization of system level bus. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinhwan Jeon, Kiyoung Choi |
Loop Pipelining in Hardware-Software Partitioning. |
ASP-DAC |
1998 |
DBLP BibTeX RDF |
|
| 1 | Youngsoo Shin, Kiyoung Choi |
Rate Assignment for Embedded Reactive Real-Time Systems. |
EUROMICRO |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungjoo Yoo, Kiyoung Choi |
Optimistic distributed timed cosimulation based on thread simulation model. |
CODES |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Dongwan Shin, Kiyoung Choi |
Low power high level synthesis by increasing data correlation. |
ISLPED |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Daehong Kim, Kiyoung Choi |
Power-conscious High Level Synthesis Using Loop Folding. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngsoo Shin, Kiyoung Choi |
Enforcing Schedulability of Multi-Task Systems by Hardware-Software Codesign. |
CODES |
1997 |
DBLP DOI BibTeX RDF |
schedulability, real-time, deadline, Codesign, rate-monotonic scheduling |
| 1 | KiJong Lee, Kiyoung Choi |
Self-timed divider based on RSD number system. |
IEEE Trans. VLSI Syst. |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungjoo Yoo, Jinhwan Jeon, Seongsoo Hong, Kiyoung Choi |
Hardware-Software Codesign of Resource-Constrained Real-Time Systems. |
RTCSA |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Youngsoo Shin, Kiyoung Choi |
Software synthesis through task decomposition by dependency analysis. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
CDFG, scheduler, dependency, C, VHDL, thread, Software synthesis |
| 1 | Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha |
An integrated hardware-software cosimulation environment for heterogeneous systems prototyping. |
ASP-DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Yongjoo Kim, Youngsoo Shin, Kyuseok Kim, Jae-Hee Won, Kiyoung Choi |
Efficient Prototyping System Based on Incremental Design and Module-by-Module Verification. |
ISCAS |
1995 |
DBLP BibTeX RDF |
|
| 1 | Kiyoung Choi, KiJong Lee, Jun-Woo Kang |
A Self-Timed Divider Using RSD Number System. |
ICCD |
1994 |
DBLP BibTeX RDF |
|
| 1 | Sun Young Hwang, Tom Blank, Kiyoung Choi |
Fast functional simulation: an incremental approach. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1988 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiyoung Choi, Sun Young Hwang, Tom Blank |
Incremental-in-time Algorithm for Digital Simulation. |
DAC |
1988 |
DBLP BibTeX RDF |
|
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