Search results for "Koichi Ishida"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai	A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai	Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and ${\rm V}_{\rm TH}$-Tuned Oscillator With Fixed Charge Programming.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, Takayasu Sakurai	Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai	A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Xin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Takayasu Sakurai, Makoto Takamiya	A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai	0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai	0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai	User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai	100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifier.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai	A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Xin Zhang, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai	An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai	Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai	Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection.	J. Solid-State Circuits	2010	DBLP DOI BibTeX RDF
1	Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai	0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
1	Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuaki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai	0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS.	CICC	2010	DBLP DOI BibTeX RDF
1	Naoki Masunaga, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai	EMI Camera LSI (EMcam) with 12 × 4 on-chip loop antenna matrix in 65-nm CMOS to measure EMI noise distribution with 60-µm spatial precision.	CICC	2010	DBLP DOI BibTeX RDF
1	Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai	User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects.	ISSCC	2010	DBLP DOI BibTeX RDF
1	Koichi Ishida, Koichi Takemura, Kazuhiro Baba, Makoto Takamiya, Takayasu Sakurai	3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's.	3DIC	2010	DBLP DOI BibTeX RDF
1	Makoto Takamiya, Koichi Ishida, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai	Design of large area electronics with organic transistors.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai	A 100 Mbps, 4.1 pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90 nm CMOS.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories.	ISLPED	2009	DBLP DOI BibTeX RDF	boost converter, inductor design, SSD, charge pump
1	Katsuyuki Ikeuchi, Kosuke Sakaida, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya	Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test.	CICC	2009	DBLP DOI BibTeX RDF
1	Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai	A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS.	ISSCC	2009	DBLP DOI BibTeX RDF
1	Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD.	ISSCC	2009	DBLP DOI BibTeX RDF
1	Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai	A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi	Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories.	3DIC	2009	DBLP DOI BibTeX RDF
1	Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai	Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.	ISQED	2008	DBLP DOI BibTeX RDF
1	Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai	Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, Takayasu Sakurai	An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai	A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression.	ASP-DAC	2006	DBLP DOI BibTeX RDF

Publications of "Koichi Ishida" ( http://dblp.L3S.de/Authors/Koichi_Ishida )