Search results for "Kolin Paul"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Syed M. A. H. Jafri, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, Hannu Tenhunen	Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation.	PECCS	2012	DBLP BibTeX RDF
1	Tapas Kumar Kundu, Kolin Paul	Analyzing and Improving Performance and Energy Efficiency of Android.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Rajeswari Devadoss, Kolin Paul, M. Balakrishnan	p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata.	JETC	2011	DBLP DOI BibTeX RDF
1	Rajeswari Devadoss, Kolin Paul, M. Balakrishnan	Architecture and tools for programmable QCA.	FPT	2011	DBLP DOI BibTeX RDF
1	Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen	Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures.	FPT	2011	DBLP DOI BibTeX RDF
1	Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen	Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Pei Liu, Ahmed Hemani, Kolin Paul	A Reconfigurable Processor for Phylogenetic Inference.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Tapas Kumar Kundu, Kolin Paul	Improving Android Performance and Energy Efficiency.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Pei Liu, Fatemeh O. Ebrahim, Ahmed Hemani, Kolin Paul	A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics.	ReConFig	2011	DBLP DOI BibTeX RDF
1	Rajeswari Devadoss, Kolin Paul, M. Balakrishnan	A tiled programmable fabric using QCA.	FPT	2010	DBLP DOI BibTeX RDF
1	Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul	A high-level synthesis flow for custom instruction set extensions for application-specific processors.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Kolin Paul, Tapas Kumar Kundu	Android on Mobile Devices: An Energy Perspective.	CIT	2010	DBLP DOI BibTeX RDF	Dalvik JVM, Android Energy
1	Rajeswari Devadoss, Kolin Paul, M. Balakrishnan	Clocking-Based Coplanar Wire Crossing Scheme for QCA.	VLSI Design	2010	DBLP DOI BibTeX RDF	Quantum Cellular Automata, Wire Crossing, Coplanar, Low Power, Clocking, Crossover, QCA, Quantum-dot Cellular Automata
1	Nagaraju Pothineni, Anshul Kumar, Kolin Paul	A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Nagaraju Pothineni, Anshul Kumar, Kolin Paul	Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Nagaraju Pothineni, Anshul Kumar, Kolin Paul	Recurring Pattern Identification and its Application to Instruction Set Extension.	CDES	2007	DBLP BibTeX RDF
1	Kolin Paul, Joel Porquet, Josep Llosa	Silicon Compaction/Defragmentation for Partial Runtime Reconfiguration.	DSD	2007	DBLP DOI BibTeX RDF
1	Nagaraju Pothineni, Anshul Kumar, Kolin Paul	Application Specific Datapath Extension with Distributed I/O Functional Units.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Rahul Jain, Anindita Mukherjee, Kolin Paul	Defect-Aware Design Paradigm for Reconfigurable Architectures.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Nilesh Padhariya, Kolin Paul, Dheeraj Bhardwaj	A FLOPs Based Model for Performance Analysis and Scheduling of Applications for Single and Multiple CPUs.	ICPP Workshops	2006	DBLP DOI BibTeX RDF
1	Sanjay V. Rajopadhye, Kolin Paul	A 1.5-D Architecture for Back-Propagation Training.	ERSA	2005	DBLP BibTeX RDF
1	Kolin Paul	An FPGA Based Test Bed for Bio Inspired Computation.	IPDPS	2005	DBLP DOI BibTeX RDF
1	Kolin Paul, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri	Theory of Extended Linear Machines.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Linear Machine (LM), Extended Linear Machine (ELM), vector subspace, extension rield, vector space
1	Kolin Paul, Ranadeep Ghosal, Biplab K. Sikdar, Santashil Pal Chaudhuri, Dipanwita Roy Chowdhury	GF(2p) CA Based Vector Quantization for Fast Encoding of Still Images.	VLSI Design	2000	DBLP DOI BibTeX RDF
1	Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee	Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator.	VLSI Design	2000	DBLP DOI BibTeX RDF	Extension field, BIST structure, Cellular Automata (CA), VLSI design and RTL, Finite field, DFT, Fault coverage, LFSR
1	Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury, Kolin Paul, Biplab K. Sikdar	Theory and Applications of Cellular Automata for VLSI Design and Testing.	VLSI Design	2000	DBLP BibTeX RDF
1	Kolin Paul, Dipanwita Roy Chowdhury	Application of GF(2p) CA in Burst Error Correcting Codes.	VLSI Design	2000	DBLP DOI BibTeX RDF
1	Kolin Paul, Parimal Pal Chaudhuri, Dipanwita Roy Chowdhury	Scalable Pipelined Micro-Architecture for Wavelet Transform.	VLSI Design	2000	DBLP DOI BibTeX RDF
1	Kolin Paul, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri	Cellular Automata Based Transform Coding for Image Compression.	HiPC	1999	DBLP DOI BibTeX RDF
1	Kolin Paul, P. Dutta, Dipanwita Roy Chowdhury, Prasanta Kumar Nandi, Parimal Pal Chaudhuri	A VLSI Architecture for On-Line Image Decompression Using GF(28) Cellular Automata.	VLSI Design	1999	DBLP BibTeX RDF
1	Kolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri	Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis. (PDF / PS)	Asian Test Symposium	1998	DBLP DOI BibTeX RDF

Publications of "Kolin Paul" ( http://dblp.L3S.de/Authors/Kolin_Paul )