Search results for "Konstantinos Masselos"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung	Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization.	Comput. J.	2011	DBLP DOI BibTeX RDF
1	Nikolaos Kavvadias, Konstantinos Masselos	Efficient Hardware Looping Units for FPGAs.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Georgia Kalogeridou, Nikolaos S. Voros, Konstantinos Masselos	System Level Design of Complex Hardware Applications Using ImpulseC.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Theodoros Lioris, Grigoris Dimitroulakos, Kostas Masselos	XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung	Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung	Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung	Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework.	FPL	2008	DBLP DOI BibTeX RDF
1	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung	Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation.	BCS Int. Acad. Conf.	2008	DBLP BibTeX RDF
1	Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung	Outer Loop Pipelining for Application Specific Datapaths in FPGAs.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Maria E. Angelopoulou, Kostas Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos	Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	5/3 lifting filter-pair, row-column, line-based, FPGA, implementation, discrete wavelet transform, comparison, lifting scheme, block-based
1	Konstantinos Masselos, Nikolaos S. Voros	Implementation of Wireless Communications Systems on FPGA-Based Platforms.	EURASIP J. Emb. Sys.	2007	DBLP DOI BibTeX RDF
1	Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung	Automatic On-chip Memory Minimization for Data Reuse.	FCCM	2007	DBLP DOI BibTeX RDF
1	Nikos S. Voros, Konstantinos Masselos	Prototyping of a WLAN system using C++ based architecture exploration.	MobiMedia	2007	DBLP DOI BibTeX RDF	hardware/software codesign, wireless systems, architecture exploration
1	Konstantinos Masselos, George A. Constantinides, Qiang Liu	Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm.	FPL	2006	DBLP DOI BibTeX RDF
1	Konstantinos Masselos, Kari Tiensyrjä, Yang Qu, Nikos S. Voros, Miroslav Cupák, Luc Rijnders, Marko Pettissalo	System Level Architecture Exploration for Reconfigurable Systems On Chip.	FPL	2006	DBLP DOI BibTeX RDF
1	Kieron Turkington, Konstantinos Masselos, George A. Constantinides, Philip Heng Wai Leong	FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach.	FPL	2006	DBLP DOI BibTeX RDF
1	Kostas Masselos, Yiannis Andreopoulos, Thanos Stouraitis	Execution time comparison of lifting-based 2D wavelet transforms implementations on a VLIW DSP.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Nikolaos S. Voros, Colin F. Snook, Stefan Hallerstede, Konstantinos Masselos	Embedded System Design Using Formal Model Refinement: An Approach Based on the Combined Use of UML and the B Language.	Design Autom. for Emb. Sys.	2004	DBLP DOI BibTeX RDF
1	Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man	Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	low-power-dissipation, performance, memory, VLIW processors, multi-media, code transformations, subword parallelism, system level
1	Yang Qu, Kari Tiensyrjä, Kostas Masselos	System-Level Modeling of Dynamically Reconfigurable Co-processors.	FPL	2004	DBLP DOI BibTeX RDF
1	Kostas Masselos, Spyros Blionas, Jean-Yves Mignolet, A. Foster, Dimitrios Soudris, Spiridon Nikolaidis	Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip Platform.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Kari Tiensyrjä, Miroslav Cupák, Kostas Masselos, Marko Pettissalo	SystemC and OCAPI-xl Based System-Level Design for Reconfigurable Systems-on-Chip.	FDL	2004	DBLP BibTeX RDF
1	Evaggelia Theochari, Konstantinos Tatas, Dimitrios Soudris, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas, Antonios Thanailakis	A reusable IP FFT core for DSP applications.	ISCAS	2004	DBLP DOI BibTeX RDF
1	Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man	Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications.	Design Autom. for Emb. Sys.	2003	DBLP DOI BibTeX RDF
1	Kostas Masselos, Antti Pelkonen, Miroslav Cupák, Spyros Blionas	Realization of wireless multimedia communication systems on reconfigurable platforms.	Journal of Systems Architecture	2003	DBLP DOI BibTeX RDF
1	Kostas Masselos, Panagiotis Merakos, S. Theoharis, Thanos Stouraitis, Constantinos E. Goutis	Power efficient data path synthesis of sum-of-products computations.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Yiannis Andreopoulos, Peter Schelkens, Gauthier Lafruit, Kostas Masselos, Jan Cornelis	High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	discrete wavelet transform implementations, cache memories, theoretical modeling
1	Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas	Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms.	PATMOS	2003	DBLP DOI BibTeX RDF
1	Antti Pelkonen, Kostas Masselos, Miroslav Cupák	System-Level Modeling of Dynamically Reconfigurable Hardware with SystemC.	IPDPS	2003	DBLP DOI BibTeX RDF
1	Konstantinos Masselos, Spyros Theoharis, Panagiotis Merakos, Thanos Stouraitis, Costas E. Goutis	Memory accesses reordering for interconnect power reduction in sum-of-products computations.	IEEE Transactions on Signal Processing	2002	DBLP DOI BibTeX RDF
1	Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man	A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Spyros Blionas, Kostas Masselos, Chrissavgi Dre, Christos Drosos, F. Z. Ieromnimon, T. Pagonis, A. Pneymatikakis, Anna Tatsaki, T. Trimis, A. Vontzalidis, Dimitris Metafas	A HIPERLAN/2 - IEEE 802.11a Reconfigurable System-on-Chip.	FPL	2002	DBLP DOI BibTeX RDF
1	George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Spyros Blionas, Kostas Masselos, Adonios Thanailakis	Architecture Design of a Reconfigurable Multiplier for Flexible Coarse-Grain Implementations.	FPL	2002	DBLP DOI BibTeX RDF
1	Kostas Masselos, Panagiotis Merakos, Constantinos E. Goutis	Power Efficient Vector Quantization Design Using Pixel Truncation.	PATMOS	2002	DBLP DOI BibTeX RDF
1	Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis	Low power architectures for digital signal processing.	Journal of Systems Architecture	2000	DBLP DOI BibTeX RDF
1	Kostas Masselos, Koen Danckaert, Francky Catthoor, Nikolaos D. Zervas, Constantinos E. Goutis, Hugo De Man	A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints.	VLSI Signal Processing	2000	DBLP DOI BibTeX RDF	processor partitioning, memory cost, performance constraints, multi-media, code transformations
1	Kostas Masselos, S. Theoharis, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis	Low power synthesis of sum-of-products computation (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF
1	Koen Danckaert, Kostas Masselos, Francky Catthoor, Hugo De Man	Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec.	Journal of Systems Architecture	1999	DBLP DOI BibTeX RDF
1	Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis	Novel techniques for bus power consumption reduction in realizations of sum-of-product computation.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
1	Koen Danckaert, Kostas Masselos, Francky Catthoor, Hugo De Man, Constantinos E. Goutis	Strategy for power-efficient design of parallel systems.	IEEE Trans. VLSI Syst.	1999	DBLP DOI BibTeX RDF
1	Kostas Masselos, Koen Danckaert, Francky Catthoor, Constantinos E. Goutis, Hugo De Man	A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints.	ISLPED	1999	DBLP DOI BibTeX RDF
1	Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis	Low power synthesis of sum-of-product computation in DSP algorithms.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Nikolaos D. Zervas, Kostas Masselos, Odysseas G. Koufopavlou, Constantinos E. Goutis	Power exploration of multimedia applications realized on embedded cores.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis	Trade-Off Analysis of a Low-Power Image Coding Algorithm.	VLSI Signal Processing	1998	DBLP DOI BibTeX RDF
1	Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis	A novel algorithm for low-power image and video coding.	IEEE Trans. Circuits Syst. Video Techn.	1998	DBLP DOI BibTeX RDF

Publications of Konstantinos Masselos Kostas Masselos ( http://dblp.L3S.de/Authors/Konstantinos_Masselos )