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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5 occurrences of 5 keywords
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Results
Found 14 publication records. Showing 14 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Ransford Hyman Jr., Koustav Bhattacharya, Nagarajan Ranganathan |
Redundancy Mining for Soft Error Detection in Multicore Processors.  |
IEEE Trans. Computers  |
2011 |
DBLP DOI BibTeX RDF |
fault tolerance, Soft errors, multicore processors |
| 1 | Koustav Bhattacharya, N. Ranganathan |
Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt |
A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Koustav Bhattacharya, Nagarajan Ranganathan, Soontae Kim |
A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Koustav Bhattacharya, Nagarajan Ranganathan |
A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Koustav Bhattacharya, Nagarajan Ranganathan |
A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Koustav Bhattacharya, Nagarajan Ranganathan |
RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Ransford Hyman Jr., Koustav Bhattacharya, N. Ranganathan |
A Strategy for Soft Error Reduction in Multi Core Designs. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan |
A VLSI System Architecture for Optical Flow Computation. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Koustav Bhattacharya, Nagarajan Ranganathan |
Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Koustav Bhattacharya, Nagarajan Ranganathan |
A linear programming formulation for security-aware gate sizing. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
dynamic power variance, linear programming., path balancing, differential power analysis, gate sizing |
| 1 | Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan |
Improving the reliability of on-chip L2 cache using redundancy. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Koustav Bhattacharya, Santanu Chaudhury, Jayanta Basak |
Video Summarization: A Machine Learning Based Approach. |
ICVGIP |
2004 |
DBLP BibTeX RDF |
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| 1 | Jayanta Basak, Koustav Bhattacharya, Santanu Chaudhury |
Multi Example Based Image Retrieval: An ICA Based Approach. |
ICVGIP |
2004 |
DBLP BibTeX RDF |
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