Search results for "Kozo Kinoshita"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita	Current-based testable design of level shifters in liquid crystal display drivers.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	At-speed scan testing, Capture switching activity, X-filling, Test cube, ATPG, Low power testing
1	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita	A Novel ATPG Method for Capture Power Reduction during Scan Testing.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Hideyuki Ichihara, Toshimasa Kuchii, Masaaki Yamadate, Hideaki Sakaguchi, Hiroshi Uemura, Kozo Kinoshita	A statistical error model for image sensors and its testing.	Systems and Computers in Japan	2007	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita	A Per-Test Fault Diagnosis Method Based on the X-Fault Model.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	A New Method for Low-Capture-Power Test Generation for Scan Testing.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita	A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.	VTS	2006	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita	On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita	Fault Diagnosis of Physical Defects Using Unknown Behavior Model.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF
1	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita	Reducing Scan Shifts Using Configurations of Compatible and Folding Scan Trees.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	scan tree, logic testing, design for testability, sequential circuit
1	Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	Low-capture-power test generation for scan-based at-speed testing.	ITC	2005	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	On Low-Capture-Power Test Generation for Scan Testing.	VTS	2005	DBLP DOI BibTeX RDF
1	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita	On Configuring Scan Trees to Reduce Scan Shifts based on a Circuit Structure.	DELTA	2004	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	On per-test fault diagnosis using the X-fault model.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita	Fault Diagnosis for Physical Defects of Unknown Behaviors.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Hiroyuki Yotsuyanagi, Toshimasa Kuchii, Shigeki Nishikawa, Masaki Hashizume, Kozo Kinoshita	Reducing Scan Shifts Using Folding Scan Trees.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Masaki Hashizume, Teppei Takeda, Hiroyuki Yotsuyanagi, Takeomi Tamesada, Yukiya Miura, Kozo Kinoshita	A BIST Circuit for IDDQ Tests.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa	Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita	Built-in Self-Test for crosstalk faults in a digital VLSI.	Systems and Computers in Japan	2002	DBLP DOI BibTeX RDF
1	Kozo Kinoshita	Foreword.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF
1	Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita	On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.	ITC	2002	DBLP DOI BibTeX RDF
1	Kazuya Shimizu, Masaya Takamura, Takanori Shirai, Noriyoshi Itazaki, Kozo Kinoshita	Fault Simulation Method for Crosstalk Faults in Clock-Delayed Domino CMOS Circuits.	DELTA	2002	DBLP DOI BibTeX RDF	Clock-delayed domino circuit, Fault simulation, crosstalk fault
1	Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita	Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
1	Teppei Takeda, Masaki Hashizume, Masahiro Ichimiya, Hiroyuki Yotsuyanagi, Yukiya Miura, Kozo Kinoshita	IDDQ Sensing Technique for High Speed IDDQ Testing.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita	Built-in Self-Test for State Faults Induced by Crosstalk in Sequential Circuits. (PDF / PS)	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Kewal K. Saluja, Yuzo Takamatsu, Kozo Kinoshita	Static test compaction for IDDQ testing of bridging faults in sequential circuits.	Systems and Computers in Japan	2000	DBLP DOI BibTeX RDF
1	Toshiyuki Maeda, Kozo Kinoshita	Compaction of IDDQ Test Sequence Using Reassignment Method.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	reassignment method, weighted random vector, sequential circuit, IDDQ testing, test compaction
1	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita	Algorithms to Select IDDQ Measurement Vectors for Bridging Faults in Sequential Circuits.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	IDDQ measurement vector, sequential circuit, bridging fault, IDDQ testing
1	Toshiyuki Maeda, Kozo Kinoshita	Precise test generation for resistive bridging faults of CMOS combinational circuits.	ITC	2000	DBLP DOI BibTeX RDF
1	Yann Antonioli, Tsuneo Inufushi, Shigeki Nishikawa, Kozo Kinoshita	A high-speed IDDQ sensor implementation.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit feedback, high-speed IDDQ sensor implementation, submicron CMOS process, feedback scheme, floppy-disk controller IDDQ test, current sensor, built-in sensor, 0.35 micron, 50 MHz, integrated circuit testing, CMOS digital integrated circuits, BICS, electric current measurement, electric sensing devices
1	Yoshinobu Higami, Yuzo Takamatsu, Kozo Kinoshita	Test sequence compaction for sequential circuits with reset states.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	reset states, test compaction method, single stuck-at fault assumption, unremovable vectors, fault-dropping fault simulation, nonfault-dropping fault simulation, reset signal, test subsequences, logic testing, fault detection, sequential circuits, sequential circuits, automatic test pattern generation, fault simulation, vectors, logic simulation, logic simulation, benchmark circuits, test vectors, signal detection, test sequence compaction
1	Toshiyuki Maeda, Kozo Kinoshita	Memory reduction of I/sub DDQ/ test compaction for internal and external bridging faults.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	I/sub DDQ/ test compaction, internal bridging faults, external bridging faults, IDDQ test sequence, reassignment method, weighted random sequences, logic testing, integrated circuit testing, sequential circuits, sequential circuits, automatic testing, fault simulation, CMOS logic circuits, CMOS circuits, test application time reduction, memory reduction
1	Arabi Keshk, Yukiya Miura, Kozo Kinoshita	Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit oscillations, transistor level networks, feedback oscillation, Byzantine General's problems, logic threshold, logic testing, logic testing, integrated circuit testing, fault coverage, fault location, bridging fault, CMOS circuits, CMOS digital integrated circuits, test vector
1	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita	Fault models and test generation for IDDQ testing: embedded tutorial.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy	Test Transformation to Improve Compaction by Statistical Encoding.	VLSI Design	2000	DBLP DOI BibTeX RDF	statistical code, fault simulation, test compression
1	Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita	Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	sequential circuit, fault simulation, bridging fault, IDDQ testing
1	Arabi Keshk, Kozo Kinoshita, Yukiya Miura	IDDQ Current Dependency on Test Vectors and Bridging Resistance.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Bridging fault, IDDQ Testing
1	Arabi Keshk, Kozo Kinoshita, Yukiya Miura	Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	Byzantine General's problem, Bridging fault
1	Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara	On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	IDDQ testing, test compaction
1	Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara	On Test Generation with A Limited Number of Tests.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita	Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits.	VLSI Design	1999	DBLP BibTeX RDF
1	Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita	An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita	Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Masaki Hashizume, Yukiya Miura, Masahiro Ichimiya, Takeomi Tamesada, Kozo Kinoshita	A High-Speed IDDQ Sensor for Low-Voltage ICs.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Tooru Honzawa, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita	Design for Diagnosability of CMOS Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita	Observation Time Reduction for IDDQ Testing of Briding Faults in Sequential Circuits.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Hiroyuki Yotsuyanagi, Kozo Kinoshita	Undetectable Fault Removal of Sequential Circuits Based on Unreachable States. (PDF / PS)	VTS	1998	DBLP DOI BibTeX RDF
1	Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita	A diagnosis method for single logic design errors in gate-level combinational circuits.	Systems and Computers in Japan	1997	DBLP DOI BibTeX RDF
1	Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara	On invariant implication relations for removing partial circuits.	Systems and Computers in Japan	1997	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	IDDQ test vector selection for transistor short fault testing.	Systems and Computers in Japan	1997	DBLP DOI BibTeX RDF
1	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Synthesis of Sequential Circuits by Redundancy Removal and Retiming.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	synthesis of sequential circuits, sequentially redundant fault, retiming, redundant fault, redundancy removal
1	Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita	An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test generation, synchronous sequential circuit, Crosstalk fault
1	Hideyuki Ichihara, Kozo Kinoshita	On Acceleration of Logic Circuits Optimization Using Implication Relations.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	logic synthesis, implication, logic optimization, recursive learning
1	Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy	A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.	VLSI Design	1997	DBLP DOI BibTeX RDF	robust dependent path, local circuit analysis, logic circuit testing, functionally unsensitizable path, timing, logic circuits
1	Yoshinobu Higami, Kozo Kinoshita	Design of partially parallel scan chain.	ED&TC	1997	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
1	Noriyoshi Itazaki, Yasutaka Idomoto, Kozo Kinoshita	A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits.	FTCS	1996	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kozo Kinoshita, Hideo Tamamoto, Hiroshi Yokoyama	Efficient Guided-Probe Fault Location Method for Sequential Circuits.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Seiji Kajihara, Rikiya Nishigaya, Tetsuji Sumioka, Kozo Kinoshita	Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	Testing of k-FR Circuits under Highly Observable Condition.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy	Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partial scan design and test sequence generation based on reduced scan shift method.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	partial scan circuit, short test sequence, reduced scan shift, scan design, test sequence generation
1	Xiaoqing Wen, Hideo Tamamoto, Kozo Kinoshita	Transistor leakage fault location with ZDDQ measurement.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	field effect transistor circuits, transistor leakage fault location, I/sub DDQ/ measurement, equivalence fault collapsing, diagnosed faults, gate-array circuit, fault diagnosis, logic testing, random tests, fault location, CMOS logic circuits, leakage currents, logic arrays, CMOS circuit, deterministic tests, electric current measurement, diagnostic resolution
1	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Test sequence compaction by reduced scan shift and retiming.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	reduced scan shift, full scan designed circuits, computational complexity, logic testing, transformation, timing, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
1	Hiroaki Ueda, Kozo Kinoshita	Low power design and its testability.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	power reduction tool, power dissipation factor, testability parameters, fault diagnosis, logic testing, delays, probability, design for testability, low power design, logic CAD, testability, fault location, stuck-at faults, CMOS logic circuits, delay faults, CMOS circuit, PORT, automatic test software, redundant faults, transition probability
1	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Resynthesis for sequential circuits designed with a specified initial state.	VTS	1995	DBLP DOI BibTeX RDF	specified initial state, retiming method, redundancy removal method, resynthesized circuit, input sequences, logic optimisation, timing, redundancy, sequential circuits, logic CAD, flip-flops, flip-flops, circuit optimisation, synchronous sequential circuits
1	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Synthesis for Testability by Sequential Redundancy Removal Using Retiming.	FTCS	1995	DBLP DOI BibTeX RDF
1	Antonio Rubio, Noriyoshi Itazaki, Xiaole Xu, Kozo Kinoshita	An approach to the analysis and detection of crosstalk faults in digital VLSI circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Reduced Scan Shift: A New Testing Method for Sequential Circuit.	ITC	1994	DBLP DOI BibTeX RDF
1	Yukiya Miura, Sachio Naito, Kozo Kinoshita	A Case Study of Mixed-Signal Integrated Circuit Testing: An Application of Current Testing Using the Upper Limit and the Lower Limit.	ISCAS	1994	DBLP BibTeX RDF
1	Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy	Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits.	DAC	1993	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita	Test generation for multiple faults based on parallel vector pair analysis.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kozo Kinoshita	A Testable Design of Logic Circuits under Highly Observable Condition.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	highly observable condition, fault tolerant computing, logic testing, integrated circuit testing, combinational circuit, stuck-at faults, logic circuits, integrated logic circuits, combinatorial circuits, stuck-open faults, testable design
1	Xiaoqing Wen, Kozo Kinoshita	Testable Designs of Sequential Circuits Under Highly Observable Condition.	ITC	1992	DBLP DOI BibTeX RDF
1	Yukiya Miura, Kozo Kinoshita	Circuit Design for Built-in Current Testing.	ITC	1992	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Haruko Shiba, Kozo Kinoshita	Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults.	FTCS	1992	DBLP DOI BibTeX RDF
1	Yuzo Takamatsu, Kozo Kinoshita	Extended selection of switching target faults in CONT algorithm for test generation.	J. Electronic Testing	1990	DBLP DOI BibTeX RDF	fault target switching, fault simulation, D-algorithm
1	Etienne Sicard, Kozo Kinoshita	On the evaluation of process-fault tolerance ability of CMOS integrated circuits.	ITC	1990	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kozo Kinoshita	A testable design of logic circuits under highly observable condition.	ITC	1990	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kozo Kinoshita	Fault detection and diagnosis of k-UCP circuits under totally observable condition.	FTCS	1990	DBLP DOI BibTeX RDF
1	Noriyoshi Itazaki, Kozo Kinoshita	Test pattern generation for circuits with tri-state modules by Z-algorithm.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
1	Yuzo Takamatsu, Kozo Kinoshita	CONT: a concurrent test generation system.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
1	Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita	Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability.	ITC	1989	DBLP DOI BibTeX RDF
1	Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita	Row/column pattern sensitive fault detection in RAMs via built-in self-test.	FTCS	1989	DBLP DOI BibTeX RDF
1	Kozo Kinoshita, Kewal K. Saluja	Built-In Testing of Memory Using an On-Chip Compact Testing Scheme.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	weight-sensitive faults, random- access memory (RAM), Built-in self-testing (BIST), stuck-at faults, built-in testing (BIT), pattern-sensitive faults, hardware complexity
1	Noriyoshi Itazaki, Kozo Kinoshita	Test Pattern Generation for Circuits with Three-state Modules by Improved Z-algorithm.	ITC	1986	DBLP BibTeX RDF
1	Kewal K. Saluja, Kozo Kinoshita	Test Pattern Generation for API Faults in RAM.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	static pattern-sensitive faults, fault detection, Built-in testing, random-access memory, pattern-sensitive faults
1	C. Boswell, Kewal K. Saluja, Kozo Kinoshita	Design of Programmable Logic Arrays for Parallel Testing.	Comput. Syst. Sci. Eng.	1985	DBLP BibTeX RDF
1	Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita	A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead.	ITC	1985	DBLP BibTeX RDF
1	Kozo Kinoshita, Kewal K. Saluja	Built-in Testing of Memory Using On-chip Compact Testing Scheme.	ITC	1984	DBLP BibTeX RDF
1	Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara	An Easily Testable Design of Programmable Logic Arrays for Multiple Faults.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	stuck-type faults, Cross-point faults, easily testable design, programmable logic arrays, multiple faults
1	Takuji Okamoto, Hiroyuki Shibata, Kozo Kinoshita	Design of High-Level Test Language for Digital LSI.	ITC	1983	DBLP BibTeX RDF
1	Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara	Test generation for scan design circuits with tri-state modules and bidirectional terminals.	DAC	1983	DBLP BibTeX RDF
1	Hideo Fujiwara, Kozo Kinoshita	A Design of Programmable Logic Arrays with Universal Tests.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Easily testable design, programmable logic arrays (PLA's), fault detection, fault location, logic circuits, universal test sets
1	Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita	An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2.	DAC	1981	DBLP BibTeX RDF
1	Tsutomu Sasao, Kozo Kinoshita	Conservative Logic Elements and Their Universality.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	universality of logic elements, logic elements, magnetic bubble logic elements, Logic circuits
1	Tsutomu Sasao, Kozo Kinoshita	On the Number of Fanout-Free Functions and Unate Cascade Functions.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	disjunctive networks, enumeration of equivalence classes, enumeration of switching functions, fanout-free function, Cascade, threshold function, unate function
1	Hideo Fujiwara, Kozo Kinoshita	Connection Assignments for Probabilistically Diagnosable Systems.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	testing links, Automatic diagnosis, probabilistic fault diagnosis, graphs, digital systems, connection assignments, self-diagnosable systems
1	Hideo Fujiwara, Kozo Kinoshita	Some Existence Theorems for Probabilistically Diagnosable Systems.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	testing links, Automatic diagnosis, probabilistic fault diagnosis, probability of failure, graphs, digital systems, self-diagnosable systems

Publications of "Kozo Kinoshita" ( http://dblp.L3S.de/Authors/Kozo_Kinoshita )