Search results for "Krste Asanovic"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic	Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators.	ISCA	2011	DBLP DOI BibTeX RDF
1	Krste Asanovic, Ralph Wittig	Guest Editors' Introduction: Hot Chips 21.	IEEE Micro	2010	DBLP DOI BibTeX RDF	parallel computing, multicore, microprocessors, hardware, accelerators, MEMS
1	Heidi Pan, Benjamin Hindman, Krste Asanovic	Composing parallel software efficiently with lithe.	PLDI	2010	DBLP DOI BibTeX RDF	cooperative scheduling, oversubscription, user-level scheduling, parallelism, resource management, composability, hierarchical scheduling
1	Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic	Re-architecting DRAM memory systems with monolithically integrated silicon photonics.	ISCA	2010	DBLP DOI BibTeX RDF	dram architecture, energy-efficiency, silicon photonics
1	Zhangxi Tan, Andrew Waterman, Henry Cook, Sarah Bird, Krste Asanovic, David A. Patterson	A case for FAME: FPGA architecture model execution.	ISCA	2010	DBLP DOI BibTeX RDF	simulation, fpga, microprocessors
1	Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson, Krste Asanovic	RAMP gold: an FPGA-based architecture simulator for multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	simulation, FPGA, multiprocessors
1	Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos Popovic, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanovic, Krste Asanovic	Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics.	IEEE Micro	2009	DBLP DOI BibTeX RDF
1	Krste Asanovic, Rastislav Bodík, James Demmel, Tony Keaveny, Kurt Keutzer, John Kubiatowicz, Nelson Morgan, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel, Katherine A. Yelick	A view of the parallel computing landscape.	Commun. ACM	2009	DBLP DOI BibTeX RDF
1	Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Scott Beamer, Imran Shamim, Krste Asanovic, Vladimir Stojanovic	Silicon-photonic clos networks for global on-chip communication.	NOCS	2009	DBLP DOI BibTeX RDF
1	Scott Beamer, Krste Asanovic, Christopher Batten, Ajay Joshi, Vladimir Stojanovic	Designing multi-socket systems using silicon photonics.	ICS	2009	DBLP DOI BibTeX RDF	multi-socket, silicon photonics
1	Ronny Krashinsky, Christopher Batten, Krste Asanovic	Implementing the scale vector-thread processor.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	hybrid C++/Verilog simulation, iterative VLSI design flow, procedural datapath pre-placement, vector-thread processors, multithreaded processors, Vector processors
1	Jae W. Lee, Man Cheuk Ng, Krste Asanovic	Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks.	ISCA	2008	DBLP DOI BibTeX RDF
1	Patrick Schaumont, Krste Asanovic, James C. Hoe	MEMOCODE 2008 Co-Design Contest.	MEMOCODE	2008	DBLP DOI BibTeX RDF
1	Mark Hampton, Krste Asanovic	Compiling for vector-thread architectures.	CGO	2008	DBLP DOI BibTeX RDF	compilers, code generation, vector processors
1	Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos Popovic, Hanqing Li, Henry I. Smith, Judy L. Hoyt, Franz X. Kärtner, Rajeev J. Ram, Vladimir Stojanovic, Krste Asanovic	Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics.	Hot Interconnects	2008	DBLP DOI BibTeX RDF
1	John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic	RAMP: Research Accelerator for Multiple Processors.	IEEE Micro	2007	DBLP DOI BibTeX RDF	field-programmable gate arrays, distributed systems, integration, parallel architectures, transactional memory, emulation, distributed-shared memory, hardware-software codesign, modeling of computer architecture
1	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Jae W. Lee, Myron King, Krste Asanovic	Continual hashing for efficient fine-grain state inconsistency detection.	ICCD	2007	DBLP DOI BibTeX RDF
1	C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie	Unbounded Transactional Memory.	IEEE Micro	2006	DBLP DOI BibTeX RDF	unbounded transactional memory, Transactional memory
1	Kenneth C. Barr, Krste Asanovic	Energy-aware lossless data compression.	ACM Trans. Comput. Syst.	2006	DBLP DOI BibTeX RDF	low-power, Compression, power-aware, energy-aware, lossless
1	Kenneth C. Barr, Krste Asanovic	Branch trace compression for snapshot-based simulation.	ISPASS	2006	DBLP DOI BibTeX RDF
1	Rose F. Liu, Krste Asanovic	Accelerating architectural exploration using canonical instruction segments.	ISPASS	2006	DBLP DOI BibTeX RDF
1	Mark Hampton, Krste Asanovic	Implementing virtual memory in a vector processor with software restart markers.	ICS	2006	DBLP DOI BibTeX RDF	exception handling, vector processors
1	Jae W. Lee, Krste Asanovic	METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors.	IEEE Real Time Technology and Applications Symposium	2006	DBLP DOI BibTeX RDF
1	Heidi Pan, Krste Asanovic, Robert Cohn, Chi-Keung Luk	Controlling program execution through binary instrumentation.	SIGARCH Computer Architecture News	2005	DBLP DOI BibTeX RDF
1	Jessica H. Tseng, Krste Asanovic	A Speculative Control Scheme for an Energy-Efficient Banked Register Fil.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	speculative control, Low-power, superscalar, register file, simultaneous multithreading
1	Michael Zhang, Krste Asanovic	Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors.	ISCA	2005	DBLP DOI BibTeX RDF
1	Kenneth C. Barr, Heidi Pan, Michael Zhang, Krste Asanovic	Accelerating Multiprocessor Simulation with a Memory Timestamp Record.	ISPASS	2005	DBLP DOI BibTeX RDF
1	Seongmoo Heo, Krste Asanovic	Replacing global wires with an on-chip network: a power analysis.	ISLPED	2005	DBLP DOI BibTeX RDF	on-chip network power model, tile size, wire power model, pipelining, router, tiled architecture
1	Emmett Witchel, Junghwan Rhee, Krste Asanovic	Mondrix: memory isolation for linux using mondriaan memory protection.	SOSP	2005	DBLP DOI BibTeX RDF	fine-grained memory protection
1	C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie	Unbounded Transactional Memory.	HPCA	2005	DBLP DOI BibTeX RDF
1	Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic	The Vector-Thread Architecture.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic	The Vector-Thread Architecture.	ISCA	2004	DBLP DOI BibTeX RDF
1	Seongmoo Heo, Krste Asanovic	Power-optimal pipelining in deep submicron technology.	ISLPED	2004	DBLP DOI BibTeX RDF	power scaling, supply voltage reduction, pipelining
1	Christopher Batten, Ronny Krashinsky, Steve Gerding, Krste Asanovic	Cache Refill/Access Decoupling for Vector Machines.	MICRO	2004	DBLP DOI BibTeX RDF
1	Jessica H. Tseng, Krste Asanovic	Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Seongmoo Heo, Kenneth C. Barr, Krste Asanovic	Reducing power density through activity migration.	ISLPED	2003	DBLP DOI BibTeX RDF	activity migration, temperature reduction, thermal model
1	Emmett Witchel, Krste Asanovic	Hardware Works, Software Doesn't: Enforcing Modularity with Mondriaan Memory Protection.	HotOS	2003	DBLP BibTeX RDF
1	Kenneth C. Barr, Krste Asanovic	Energy Aware Lossless Data Compression.	MobiSys	2003	DBLP BibTeX RDF
1	Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste Asanovic	Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	Dynamic Leakage Reduction
1	Michael Zhang, Krste Asanovic	Fine-grain CAM-tag cache resizing using miss tags.	ISLPED	2002	DBLP DOI BibTeX RDF	cache resizing, low-power, energy efficiency, leakage current, content-addressable-memory
1	Emmett Witchel, Josh Cates, Krste Asanovic	Mondrian memory protection.	ASPLOS	2002	DBLP DOI BibTeX RDF
1	Michael Sung, Ronny Krashinsky, Krste Asanovic	Multithreading decoupled architectures for complexity-effective general purpose computing.	SIGARCH Computer Architecture News	2001	DBLP DOI BibTeX RDF
1	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	ARVLSI	2001	DBLP DOI BibTeX RDF
1	Emmett Witchel, Samuel Larsen, C. Scott Ananian, Krste Asanovic	Direct addressed caches for reduced power consumption.	MICRO	2001	DBLP DOI BibTeX RDF
1	Heidi Pan, Krste Asanovic	Heads and tails: a variable-length instruction format supporting parallel fetch and decode.	CASES	2001	DBLP DOI BibTeX RDF
1	Luis Villa, Michael Zhang, Krste Asanovic	Dynamic zero compression for cache energy reduction.	MICRO	2000	DBLP DOI BibTeX RDF
1	Christoforos E. Kozyrakis, Stylianos Perissakis, David A. Patterson, Thomas E. Anderson, Krste Asanovic, Neal Cardwell, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Randi Thomas, Noah Treuhaft, Katherine A. Yelick	Scalable Processors in the Billion-Transistor Era: IRAM.	IEEE Computer	1997	DBLP DOI BibTeX RDF
1	Jeff Bilmes, Krste Asanovic, Chee-Whye Chin, James Demmel	Optimizing Matrix Multiply Using PHiPAC: A Portable, High-Performance, ANSI C Coding Methodology.	International Conference on Supercomputing	1997	DBLP DOI BibTeX RDF	C
1	Krste Asanovic	A Fast Kohonen Net Implementation for Spert-II.	IWANN	1997	DBLP DOI BibTeX RDF
1	David A. Patterson, Krste Asanovic, Aaron B. Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos E. Kozyrakis, David Martin, Stylianos Perissakis, Randi Thomas, Noah Treuhaft, Katherine A. Yelick	Intelligent RAM (IRAM): The Industrial Setting, Applications and Architectures.	ICCD	1997	DBLP BibTeX RDF
1	John Wawrzynek, Krste Asanovic, Brian Kingsbury, David Johnson, James Beck, Nelson Morgan	Spert-II: A Vector Microprocessor System.	IEEE Computer	1996	DBLP DOI BibTeX RDF
1	John Wawrzynek, Krste Asanovic, Brian Kingsbury, James Beck, David Johnson, Nelson Morgan	SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training.	NIPS	1995	DBLP BibTeX RDF
1	Krste Asanovic, James Beck, Jerry Feldman, Nelson Morgan, John Wawrzynek	Designing A Connectionist Network Supercomputer.	Int. J. Neural Syst.	1993	DBLP DOI BibTeX RDF
1	Krste Asanovic, Nelson Morgan, John Wawrzynek	Using simulations of reduced precision arithmetic to design a neuro-microprocessor.	VLSI Signal Processing	1993	DBLP DOI BibTeX RDF

Publications of "Krste Asanovic" ( http://dblp.L3S.de/Authors/Krste_Asanovic )