Search results for "Kunhyuk Kang"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Seung Hoon Choi, Kunhyuk Kang, Florentin Dartu, Kaushik Roy	Timed Input Pattern Generation for an Accurate Delay Calculation Under Multiple Input Switching.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Sang Phill Park, Keejong Kim, Kaushik Roy	On-Chip Variability Sensor Using Phase-Locked Loop for Detecting and Correcting Parametric Timing Failures.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Jing Li, Kunhyuk Kang, Kaushik Roy	Variation Estimation and Compensation Technique in Scaled LTPS TFT Circuits for Low-Power Low-Cost Applications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Sang Phill Park, Kunhyuk Kang, Kaushik Roy	Reliability Implications of Bias-Temperature Instability in Digital ICs.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy	NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy	Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy, Muhammad Ashraful Alam	Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy	Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Muhammad Ashraful Alam, Kaushik Roy	Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using IDDQ.	ITC	2007	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Keejong Kim, Kaushik Roy	Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop.	DAC	2007	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy	Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.	DAC	2007	DBLP DOI BibTeX RDF
1	Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy	High Performance and Low Power Electronics on Flexible Substrate.	DAC	2007	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Sang Phill Park, Kaushik Roy, Muhammad Ashraful Alam	Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Bipul C. Paul, Kaushik Roy	Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	Process variation, spatial correlation, statistical timing analysis
1	Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy	Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.	DATE	2006	DBLP DOI BibTeX RDF
1	Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy	Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI.	ICCD	2006	DBLP BibTeX RDF
1	Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy	Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring.	ITC	2005	DBLP DOI BibTeX RDF
1	Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy	Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	process variation, yield, leakage, dual-Vt, metal gate
1	Kunhyuk Kang, Bipul Chandra Paul, Kaushik Roy	Statistical Timing Analysis using Levelized Covariance Propagation.	DATE	2005	DBLP DOI BibTeX RDF
1	Amit Agarwal, Kunhyuk Kang, Kaushik Roy	Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations.	ICCAD	2005	DBLP BibTeX RDF

Publications of "Kunhyuk Kang" ( http://dblp.L3S.de/Authors/Kunhyuk_Kang )