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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5 occurrences of 4 keywords
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Results
Found 6 publication records. Showing 6 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Kyu-won Choi, Abhijit Chatterjee |
An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs.  |
ISVLSI  |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Kyu-won Choi, Abhijit Chatterjee |
UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
device and interconnect co-optimization, nanometer design, time slack distribution, low-power design |
| 1 | Kyu-won Choi, Abhijit Chatterjee |
PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Kyu-won Choi, Abhijit Chatterjee |
HA2TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
gate-level power optimization, time slack distribution, low-power design |
| 1 | Abhijit Chatterjee, Peeter Ellervee, Vincent John Mooney III, Jun-Cheol Park, Kyu-won Choi, Kiran Puttaswamy |
System Level Power-Performance Trade-Offs in Embedded Systems Using Voltage and Frequency Scaling of Off-Chip Buses and Memory. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
voltage/frequency scaling, embedded systems, design space, power-performance trade-offs |
| 1 | Kyu-won Choi, Abhijit Chatterjee |
Efficient instruction-level optimization methodology for low-power embedded systems. |
ISSS |
2001 |
DBLP BibTeX RDF |
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