Search results for "Larry T. Pileggi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Cheng-Yuan Wen, Jeyanandh Paramesh, Larry T. Pileggi, Jing Li, SangBum Kim, Jonathan Proesel, Chung Lam	Post-silicon calibration of analog CMOS using phase-change memory cells.	ESSCIRC	2011	DBLP DOI BibTeX RDF
1	Matthias Althoff, Soner Yaldiz, Akshay Rajhans, Xin Li, Bruce H. Krogh, Larry T. Pileggi	Formal verification of phase-locked loops using reachability analysis and continuization.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Gokce Keskin, Jonathan Proesel, Jean-Olivier Plouchart, Lawrence T. Pileggi	Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Soner Yaldiz, V. Calayir, Xin Li, Lawrence T. Pileggi, A. S. Natarajan, M. A. Ferriss, J. Tierno	Indirect phase noise sensing for self-healing voltage controlled oscillators.	CICC	2011	DBLP DOI BibTeX RDF
1	Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry T. Pileggi, Andrzej J. Strojwas, Jason Hibbeler	Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Gokce Keskin, Jonathan Proesel, Larry T. Pileggi	Statistical modeling and post manufacturing configuration for scaled analog CMOS.	CICC	2010	DBLP DOI BibTeX RDF
1	Alyssa Bonnoit, Lawrence T. Pileggi	Reducing variability in chip-multiprocessors with adaptive body biasing.	ISLPED	2010	DBLP DOI BibTeX RDF	dynamic voltage/frequency scaling, body biasing
1	Jonathan Proesel, Gokce Keskin, Jean-Olivier Plouchart, Lawrence T. Pileggi	An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection.	CICC	2010	DBLP DOI BibTeX RDF
1	Soner Yaldiz, Umut Arslan, Xin Li, Larry T. Pileggi	Efficient statistical analysis of read timing failures in SRAM circuits.	ISQED	2009	DBLP DOI BibTeX RDF
1	Yang Xu, Kan-Lin Hsiung, Xin Li, Lawrence T. Pileggi, Stephen P. Boyd	Regular Analog/RF Integrated Circuits Design Using Optimization With Recourse Including Ellipsoidal Uncertainty.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Alyssa Bonnoit, Sebastian Herbert, Diana Marculescu, Lawrence T. Pileggi	Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection.	ISLPED	2009	DBLP DOI BibTeX RDF	dynamic voltage / frequency scaling, body biasing
1	Jian Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi	SRAM parametric failure analysis.	DAC	2009	DBLP DOI BibTeX RDF	failure probability estimation, response surface model, SRAM, parametric failure
1	Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi	Creating an affordable 22nm node using design-lithography co-optimization.	DAC	2009	DBLP DOI BibTeX RDF	design technology co-optimization, templates, DFM, regular fabric
1	Jason G. Brown, Brian Taylor, Ronald D. Blanton, Larry T. Pileggi	Automated Testability Enhancements for Logic Brick Libraries.	DATE	2008	DBLP DOI BibTeX RDF
1	Xin Li, Yaping Zhan, Lawrence T. Pileggi	Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi	Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi	Specification Test Compaction for Analog Circuits and MEMS	CoRR	2007	DBLP BibTeX RDF
1	Brian Taylor, Larry T. Pileggi	Exact Combinatorial Optimization Methods for Physical Design of Regular Logic Bricks.	DAC	2007	DBLP DOI BibTeX RDF
1	Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi	Robust Analog/RF Circuit Design With Projection-Based Performance Modeling.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi	Asymptotic Probability Extraction for Nonnormal Performance Distributions.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif	Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction	CoRR	2007	DBLP BibTeX RDF
1	Jian Wang, Xin Li, Lawrence T. Pileggi	Parameterized Macromodeling for Analog System-Level Design Exploration.	DAC	2007	DBLP DOI BibTeX RDF
1	Xin Li, Lawrence T. Pileggi	Efficient Parametric Yield Extraction for Multiple Correlated Non-Normal Performance Distributions of Analog/RF Circuits.	DAC	2007	DBLP DOI BibTeX RDF
1	Xin Li, Brian Taylor, YuTsun Chien, Lawrence T. Pileggi	Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Xin Li, Jiayong Le, Lawrence T. Pileggi	Statistical Performance Modeling and Optimization.	Foundations and Trends in Electronic Design Automation	2006	DBLP DOI BibTeX RDF
1	Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra	IC thermal simulation and modeling via efficient multigrid-based approaches.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Xin Li, Jiayong Le, Lawrence T. Pileggi	Projection-based statistical analysis of full-chip leakage power with non-log-normal distributions.	DAC	2006	DBLP DOI BibTeX RDF	statistical analysis, leakage power
1	Padmini Gopalakrishnan, Xin Li, Lawrence T. Pileggi	Architecture-aware FPGA placement using metric embedding.	DAC	2006	DBLP DOI BibTeX RDF	FPGAs, placement, metric embedding
1	Kim Yaw Tong, Lawrence T. Pileggi	Synthesis of Regular Logic Bricks for Robust IC Design.	ICCD	2006	DBLP BibTeX RDF
1	Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi	Specification Test Compaction for Analog Circuits and MEMS.	DATE	2005	DBLP DOI BibTeX RDF
1	Peng Li, Lawrence T. Pileggi	Compact reduced-order modeling of weakly nonlinear analog and RF circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Yang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, Stephen P. Boyd, Lawrence T. Pileggi	OPERA: optimization with ellipsoidal uncertainty for robust analog IC design.	DAC	2005	DBLP DOI BibTeX RDF	optimization, statistical
1	Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma	Correlation-aware statistical timing analysis with non-gaussian delay distributions.	DAC	2005	DBLP DOI BibTeX RDF	process variation, statistical timing
1	V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi	Design methodology for IC manufacturability based on regular logic-bricks.	DAC	2005	DBLP DOI BibTeX RDF	regularity, manufacturability, integrated circuits, RET
1	Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif	Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction.	DATE	2005	DBLP DOI BibTeX RDF
1	Xin Li, Jian Wang, Lawrence T. Pileggi, Tun-Shih Chen, Wanju Chiang	Performance-centering optimization for system-level analog design exploration.	ICCAD	2005	DBLP BibTeX RDF
1	Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J. Strojwas	Projection-based performance modeling for inter/intra-die variations.	ICCAD	2005	DBLP BibTeX RDF
1	Xin Li, Peng Li, Lawrence T. Pileggi	Parameterized interconnect order reduction with explicit-and-implicit multi-parameter moment matching for inter/intra-die variations.	ICCAD	2005	DBLP BibTeX RDF
1	Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi	Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations.	ICCAD	2005	DBLP BibTeX RDF
1	Peng Li, Yangdong Deng, Lawrence T. Pileggi	Temperature-Dependent Optimization of Cache Leakage Power Dissipation.	ICCD	2005	DBLP DOI BibTeX RDF
1	Radu Marculescu, Diana Marculescu, Larry T. Pileggi	Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems.	ICCD	2004	DBLP DOI BibTeX RDF
1	Michael W. Beattie, Lawrence T. Pileggi	Parasitics extraction with multipole refinement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Satrajit Gupta, Lawrence T. Pileggi	CHIME: coupled hierarchical inductance model evaluation.	DAC	2004	DBLP DOI BibTeX RDF	inductance modeling, circuit simulation
1	Xin Li, Yang Xu, Peng Li, Padmini Gopalakrishnan, Lawrence T. Pileggi	A frequency relaxation approach for analog/RF system-level simulation.	DAC	2004	DBLP DOI BibTeX RDF	analog/RF circuits, system-level simulation
1	Yang Xu, Lawrence T. Pileggi, Stephen P. Boyd	ORACLE: optimization with recourse of analog circuits including layout extraction.	DAC	2004	DBLP DOI BibTeX RDF	optimization with recourse
1	V. Kheterpal, Andrzej J. Strojwas, Lawrence T. Pileggi	Routing architecture exploration for regular fabrics.	DAC	2004	DBLP DOI BibTeX RDF	BEOL, regularity
1	Jiayong Le, Xin Li, Lawrence T. Pileggi	STAC: statistical timing analysis with correlation.	DAC	2004	DBLP DOI BibTeX RDF	process variation, statistical timing
1	Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi	An Interconnect Channel Design Methodology for High Performance Integrated Circuits.	DATE	2004	DBLP DOI BibTeX RDF
1	Aneesh Koorapaty, V. Kheterpal, Padmini Gopalakrishnan, M. Fu, Lawrence T. Pileggi	Exploring Logic Block Granularity for Regular Fabrics.	DATE	2004	DBLP DOI BibTeX RDF
1	Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi	A power aware system level interconnect design methodology for latency-insensitive systems.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Peng Li, Lawrence T. Pileggi, Mehdi Asheghi, Rajit Chandra	Efficient full-chip thermal modeling and analysis.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi	Robust analog/RF circuit design with projection-based posynomial modeling.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Peng Li, Lawrence T. Pileggi	Efficient harmonic balance simulation using multi-level frequency decomposition.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi	Asymptotic probability extraction for non-normal distributions of circuit performance.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Global and local congestion optimization in technology mapping.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Peng Li, Lawrence T. Pileggi	Efficient per-nonlinearity distortion analysis for analog and RF circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Hui Zheng, Byron Krauter, Lawrence T. Pileggi	Electrical Modeling of Integrated-Package Power and Ground Distributions.	IEEE Design &amp; Test of Computers	2003	DBLP DOI BibTeX RDF
1	Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit	Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics.	FPL	2003	DBLP DOI BibTeX RDF
1	E. Malley, A. Salinas, K. Ismail, Lawrence T. Pileggi	Power Comparison of Throughput Optimized IC Busses.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Bounding the efforts on congestion optimization for physical synthesis.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	optimization, logic synthesis, physical design, technology mapping, routing congestion
1	Xiaoning Qi, Goetz Leonhardt, Daniel Flees, Xiao-Dong Yang, Sangwoo Kim, Stephan Mueller, Hendrik T. Mau, Lawrence T. Pileggi	A fast simulation approach for inductive effects of VLSI interconnects.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	inductance, circuit simulation, VLSI interconnects
1	Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi	An architectural exploration of via patterned gate arrays.	ISPD	2003	DBLP DOI BibTeX RDF	VPGA, lookup table, interconnect architectures, gate array
1	Abbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi	Fast, cheap and under control: the next implementation fabric.	DAC	2003	DBLP DOI BibTeX RDF
1	Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, K. Y. Tong	Exploring regular fabrics to optimize the performance-cost trade-off.	DAC	2003	DBLP DOI BibTeX RDF	performance, regularity, cost, integrated circuits
1	Xin Li, Peng Li, Yang Xu, Lawrence T. Pileggi	Analog and RF circuit macromodels for system-level analysis.	DAC	2003	DBLP DOI BibTeX RDF	analog/RF circuits, macromodel
1	Peng Li, Lawrence T. Pileggi	NORM: compact model order reduction of weakly nonlinear systems.	DAC	2003	DBLP DOI BibTeX RDF	RF circuit modeling, nonlinear model order reduction
1	Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit	Heterogeneous Programmable Logic Block Architectures.	DATE	2003	DBLP DOI BibTeX RDF
1	Yang Xu, Xin Li, Peng Li, Lawrence T. Pileggi	Noise Macromodel for Radio Frequency Integrated Circuits.	DATE	2003	DBLP DOI BibTeX RDF
1	Jiayong Le, Lawrence T. Pileggi, Anirudh Devgan	Circuit Simulation of Nanotechnology Devices with Non-monotonic I-V Characteristics.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Peng Li, Xin Li, Yang Xu, Lawrence T. Pileggi	A Hybrid Approach to Nonlinear Macromodel Generation for Time-Varying Analog Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Emrah Acar, Florentin Dartu, Lawrence T. Pileggi	TETA: transistor-level waveform evaluation for timing analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje	An analysis of the wire-load model uncertainty problem.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Michael W. Beattie, Lawrence T. Pileggi	On-chip induction modeling: basics and advanced methods.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi	Time-Domain Simulation of Variational Interconnect Models. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF	simulation, Interconnect, variational models, reduced order modeling
1	Aneesh Koorapaty, Lawrence T. Pileggi	Modular, Fabric-Specific Synthesis for Programmable Architectures.	FPL	2002	DBLP DOI BibTeX RDF
1	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Understanding and addressing the impact of wiring congestion during technology mapping.	ISPD	2002	DBLP DOI BibTeX RDF
1	Tao Lin, Michael W. Beattie, Lawrence T. Pileggi	On the efficacy of simplified 2D on-chip inductance models.	DAC	2002	DBLP DOI BibTeX RDF	PEEC, on-chip inductance, sparsified model
1	Hui Zheng, Lawrence T. Pileggi	Modeling and analysis of regular symmetrically structured power/ground distribution networks.	DAC	2002	DBLP DOI BibTeX RDF	design tegularity, folding technique, power/ground distribution, susceptance
1	Peng Li, Lawrence T. Pileggi	A Linear-Centric Modeling Approach to Harmonic Balance Analysis.	DATE	2002	DBLP DOI BibTeX RDF
1	Tao Lin, Michael W. Beattie, Lawrence T. Pileggi	On-Chip Inductance Models: 3D or Not 3D?	DATE	2002	DBLP DOI BibTeX RDF
1	Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter	Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses.	DATE	2002	DBLP DOI BibTeX RDF
1	Davide Pandini, Lawrence T. Pileggi, Andrzej J. Strojwas	Congestion-Aware Logic Synthesis.	DATE	2002	DBLP DOI BibTeX RDF
1	Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi	A Linear-Centric Simulation Framework for Parametric Fluctuations.	DATE	2002	DBLP DOI BibTeX RDF
1	Lawrence T. Pileggi, Andreas Kuehlmann (eds.)	Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002, San Jose, California, USA, November 10-14, 2002	ICCAD	2002	DBLP BibTeX RDF
1	Hui Zheng, Lawrence T. Pileggi	Robust and passive model order reduction for circuits containing susceptance elements.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Tao Lin, Lawrence T. Pileggi	Throughput-driven IC communication fabric synthesis.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Michael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi	Equipotential shells for efficient inductance extraction.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu	Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations.	ISQED	2001	DBLP DOI BibTeX RDF
1	Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje	Overcoming wireload model uncertainty during physical design.	ISPD	2001	DBLP DOI BibTeX RDF
1	Tao Lin, Lawrence T. Pileggi	RC(L) interconnect sizing with second order considerations via posynomial programming.	ISPD	2001	DBLP DOI BibTeX RDF	RC trees, VLSI design automation, central moments, posynomiality, convex programming, interconnect optimization
1	Michael W. Beattie, Lawrence T. Pileggi	Modeling Magnetic Coupling for On-Chip Interconnect.	DAC	2001	DBLP DOI BibTeX RDF
1	Michael W. Beattie, Lawrence T. Pileggi	Inductance 101: Modeling and Extraction.	DAC	2001	DBLP DOI BibTeX RDF
1	Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi	False Coupling Interactions in Static Timing Analysis.	DAC	2001	DBLP DOI BibTeX RDF
1	Yi-Chang Lu, Mustafa Celik, Tak Young, Lawrence T. Pileggi	Min/max On-Chip Inductance Models and Delay Metrics.	DAC	2001	DBLP DOI BibTeX RDF
1	Michael W. Beattie, Lawrence T. Pileggi	Efficient inductance extraction via windowing.	DATE	2001	DBLP DOI BibTeX RDF
1	Ying Liu, Sani R. Nassif, Lawrence T. Pileggi, Andrzej J. Strojwas	Impact of interconnect variations on the clock skew of a gigahertz microprocessor.	DAC	2000	DBLP DOI BibTeX RDF
1	Raul Camposano, Jacob Greidinger, Patrick Groeneveld, Michael Jackson, Lawrence T. Pileggi, Louis Scheffer	Design closure (panel session): hope or hype?	DAC	2000	DBLP DOI BibTeX RDF
1	Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi	TACO: timing analysis with coupling.	DAC	2000	DBLP DOI BibTeX RDF
1	Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi	Hierarchical Interconnect Circuit Models.	ICCAD	2000	DBLP BibTeX RDF
1	Mustafa Celik, Lawrence T. Pileggi	Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF

Publications of Larry T. Pileggi Lawrence T. Pileggi Lawrence T. Pillage ( http://dblp.L3S.de/Authors/Larry_T._Pileggi )