Search results for "Leonel Sousa"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Gabriel Falcão Paiva Fernandes, Marco Alexandre Cravo Gomes, Vítor Manuel Mendes da Silva, Leonel Sousa, Joao Cacheira	Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design.	EURASIP J. Wireless Comm. and Networking	2012	DBLP DOI BibTeX RDF
1	Leonel Sousa, Samuel Antao	Corrections to "MRC-Based RNS Reverse Converters for the Four-Moduli Sets 2n+1, 2n-1, 2n, 22n+1-1 and 2n+1, 2n-1, 22n, 22n+1-1".	IEEE Trans. on Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Leonel Sousa, Samuel Antao	MRC-Based RNS Reverse Converters for the Four-Moduli Sets 2n+1, 2n-1, 2n, 22n+1-1 and 2n+1, 2n-1, 22n, 22n+1-1.	IEEE Trans. on Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Héctor Pettenghi, Leonel Sousa, Jude Angelo Ambrose	Efficient implementation of multi-moduli architectures for Binary-to-RNS conversion.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Aleksandar Ilic, Leonel Sousa	On Realistic Divisible Load Scheduling in Highly Heterogeneous Distributed Systems.	PDP	2012	DBLP DOI BibTeX RDF
1	Aleksandar Ilic, Leonel Sousa	CHPS: An Environment for Collaborative Execution on Heterogeneous Desktop Systems.	IJNC	2011	DBLP BibTeX RDF
1	Nuno Roma, Leonel Sousa	A tutorial overview on the properties of the discrete cosine transform for encoded image and video processing.	Signal Processing	2011	DBLP DOI BibTeX RDF
1	Yves Robert, Leonel Sousa, Denis Trystram	Parallel Computing - Special Issue.	Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva	Massively LDPC Decoding on Multicore Architectures.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	graphics processing units, GPU, multicore, OpenMP, CUDA, CELL, LDPC, data-parallel computing
1	Svetislav Momcilovic, Leonel Sousa	Modeling and Evaluating Non-shared Memory CELL/BE Type Multi-core Architectures for Local Image and Video Processing.	Signal Processing Systems	2011	DBLP DOI BibTeX RDF
1	Tiago Dias, Sebastián López, Nuno Roma, Leonel Sousa	High throughput and scalable architecture for unified transform coding in embedded H.264/AVC video coding systems.	ICSAMOS	2011	DBLP DOI BibTeX RDF
1	Gabriel Falcão Paiva Fernandes, Joao Andrade, Vítor Manuel Mendes da Silva, Leonel Sousa	Real-time DVB-S2 LDPC decoding on many-core GPU accelerators.	ICASSP	2011	DBLP DOI BibTeX RDF
1	Leonel Sousa, Frédéric Suter, Alfredo Goldman, Rizos Sakellariou, Oliver Sinnen	Introduction.	Euro-Par	2011	DBLP DOI BibTeX RDF
1	Aleksandar Ilic, Leonel Sousa	Scheduling Divisible Loads on Heterogeneous Desktop Systems with Limited Memory.	Euro-Par Workshops	2011	DBLP DOI BibTeX RDF
1	Pedro Miguens Matutino, Ricardo Chaves, Leonel Sousa	Binary-to-RNS Conversion Units for moduli {2^n ± 3}.	DSD	2011	DBLP DOI BibTeX RDF
1	Paulo Alexandre Crisóstomo Lopes, José A. Germano, Teresa Mendes de Almeida, Leonel Augusto Sousa, Moisés Simões Piedade, F. A. Cardoso, H. A. Ferreira, P. P. Freitas	Measuring and Extraction of Biological Information on New Handheld Biochip-Based Microsystem.	IEEE T. Instrumentation and Measurement	2010	DBLP DOI BibTeX RDF
1	Teresa Mendes de Almeida, Moisés Simões Piedade, Leonel Augusto Sousa, José A. Germano, Paulo Alexandre Crisóstomo Lopes, F. A. Cardoso, P. P. Freitas	On the Modeling of New Tunnel Junction Magnetoresistive Biosensors.	IEEE T. Instrumentation and Measurement	2010	DBLP DOI BibTeX RDF
1	Pedro Tomás, Leonel Sousa	A quantitative analysis of firing rate estimators: Unveiling bias sources.	Neurocomputing	2010	DBLP DOI BibTeX RDF
1	Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva	Embedded multicore architectures for LDPC decoding.	ICSAMOS	2010	DBLP DOI BibTeX RDF
1	Hai-Xiang Lin, Michael Alexander, Martti Forsell, Andreas Knüpfer, Radu Prodan, Leonel Sousa, Achim Streit (eds.)	Euro-Par 2009 - Parallel Processing Workshops, HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25-28, 2009, Revised Selected Papers	Euro-Par Workshops	2010	DBLP DOI BibTeX RDF
1	Tiago Dias, Nuno Roma, Leonel Sousa	Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems.	DASIP	2010	DBLP DOI BibTeX RDF
1	Pedro Miguel Matutino, Ricardo Chaves, Leonel Sousa	Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations.	DSD	2010	DBLP DOI BibTeX RDF
1	Bruno Francisco, Frederico Pratas, Leonel Sousa	Unifying stream based and reconfigurable computing to design application accelerators.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Héctor Pettenghi, Ricardo Chaves, Leonel Sousa, Maria J. Avedillo	An improved RNS generator 2n +/- k based on threshold logic.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	António Rodrigues, Nuno Roma, Leonel Sousa	p264: open platform for designing parallel H.264/AVC video encoders on multi-core systems.	NOSSDAV	2010	DBLP DOI BibTeX RDF	h.264, parallel systems, multi-core processors, video encoder
1	Frederico Pratas, Ricardo A. Mata, Leonel Sousa	Iterative induced dipoles computation for molecular mechanics on GPUs.	GPGPU	2010	DBLP DOI BibTeX RDF	induced dipoles, molecular mechanics, polarizable force fields, parallel programing, GPGPU
1	Aleksandar Ilic, Leonel Sousa	Collaborative execution environment for heterogeneous parallel systems.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
1	Samuel Antao, Jean-Claude Bajard, Leonel Sousa	Elliptic Curve point multiplication on GPUs.	ASAP	2010	DBLP DOI BibTeX RDF
1	Rui Ramalho, Pedro Tomás, Leonel Sousa	Efficient Independent Component Analysis on a GPU.	CIT	2010	DBLP DOI BibTeX RDF	graphics processing units, Independent component analysis, eigenvalue decomposition
1	Kazeem Alagbe Gbolagade, Ricardo Chaves, Leonel Sousa, Sorin Dan Cotofana	An improved RNS reverse converter for the {22n+1-1, 2n, 2n-1} moduli set.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Samuel Antao, Leonel Sousa	Exploiting SIMD extensions for linear image processing with OpenCL.	ICCD	2010	DBLP DOI BibTeX RDF
1	Pedro Tomás, Leonel Augusto Sousa	A Feature Selection Algorithm for the Regularization of Neuron Models.	IEEE T. Instrumentation and Measurement	2009	DBLP DOI BibTeX RDF
1	João Martins, Pedro Tomás, Leonel Sousa	Neural code metrics: Analysis and application to the assessment of neural models.	Neurocomputing	2009	DBLP DOI BibTeX RDF
1	Gabriel Falcão Paiva Fernandes, Shinichi Yamagiwa, Vítor Manuel Mendes da Silva, Leonel Sousa	Parallel LDPC Decoding on GPUs Using a Stream-Based Computing Approach.	J. Comput. Sci. Technol.	2009	DBLP DOI BibTeX RDF
1	Shinichi Yamagiwa, Leonel Sousa	Modelling and programming stream-based distributed computing based on the meta-pipeline approach.	IJPEDS	2009	DBLP DOI BibTeX RDF
1	Frederico Pratas, Leonel Sousa	Applying the Stream-Based Computing Model to Design Hardware Accelerators: A Case Study.	SAMOS	2009	DBLP DOI BibTeX RDF
1	Leonel Sousa	Preface.	Euro-Par Workshops	2009	DBLP DOI BibTeX RDF
1	Svetislav Momcilovic, Leonel Sousa	Development and evaluation of scalable video motion estimators on GPU.	SiPS	2009	DBLP DOI BibTeX RDF
1	Frederico Pratas, Pedro Trancoso, Alexandros Stamatakis, Leonel Sousa	Fine-grain Parallelism Using Multi-core, Cell/BE, and GPU Systems: Accelerating the Phylogenetic Likelihood Function.	ICPP	2009	DBLP DOI BibTeX RDF
1	Samuel Antao, Ricardo Chaves, Leonel Sousa	Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable Devices.	FCCM	2009	DBLP DOI BibTeX RDF	Cryptography, Elliptic Curve, Reconfigurable Hardware, Microcode
1	Gabriel Falcão Paiva Fernandes, Vítor Manuel Mendes da Silva, Leonel Sousa	How GPUs can outperform ASICs for fast LDPC decoding.	ICS	2009	DBLP DOI BibTeX RDF	memory coalescence, parallel processing, graphics processing units, multithreading, low-density parity-check codes
1	Gesner Passos, Nuno Roma, Bertinho Andrade da Costa, Leonel Sousa, João Miranda Lemos	Distributed Software Platform for Automation and Control of General Anaesthesia.	ISPDC	2009	DBLP DOI BibTeX RDF	Biomedical equipment, Fault diagnosis, Automation, Distributed control, Control Systems
1	Leonel Sousa, Yves Robert (eds.)	Eighth International Symposium on Parallel and Distributed Computing, ISPDC 2009, Lisbon, Portugal, June 30-July 4 2009	ISPDC	2009	DBLP BibTeX RDF
1	Shinichi Yamagiwa, Leonel Sousa	CaravelaMPI: Message Passing Interface for Parallel GPU-Based Applications.	ISPDC	2009	DBLP DOI BibTeX RDF	Parallel Computing, MPI, GPU, Cluster Computing, GPGPU
1	Leonel Sousa, Svetislav Momcilovic, Vítor Manuel Mendes da Silva, Gabriel Falcão Paiva Fernandes	Multi-core platforms for signal processing: source and channel coding.	ICME	2009	DBLP DOI BibTeX RDF
1	José A. Germano, Rui Ramalho, Leonel Sousa	On the design of distributed autonomous embedded systems for biomedical applications.	PervasiveHealth	2009	DBLP DOI BibTeX RDF
1	Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva, José Marinho	Parallel LDPC Decoding on the Cell/B.E. Processor.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Gabriel Falcão Paiva Fernandes, Vítor Manuel Mendes da Silva, Marco Alexandre Cravo Gomes, Leonel Augusto Sousa	Edge Stream Oriented LDPC Decoding.	PDP	2008	DBLP DOI BibTeX RDF	LDPC decoding, Caravela, GPU, Stream architectures
1	Svetislav Momcilovic, Leonel Sousa	Parallel Advanced Video Coding: Motion Estimation on Multi-cores.	Scalable Computing: Practice and Experience	2008	DBLP BibTeX RDF
1	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	Cost-Efficient SHA Hardware Accelerators.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa	On-the-fly attestation of reconfigurable hardware.	FPL	2008	DBLP DOI BibTeX RDF
1	Pedro Miguens Matutino, Leonel Sousa	An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences.	DSD	2008	DBLP DOI BibTeX RDF
1	Nuno Sebastião, Tiago Dias, Nuno Roma, Paulo F. Flores, Leonel Sousa	Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units.	DSD	2008	DBLP DOI BibTeX RDF
1	Shinichi Yamagiwa, Leonel Sousa	Design and implementation of a tool for modeling and programming deadlock free meta-pipeline applications.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras	Low power microarchitecture with instruction reuse.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	loop reusing technique, reorder buffer optimization, superscalar processor, power reduction
1	Shinichi Yamagiwa, Koichi Wada, Leonel Sousa	Heuristic Optimization Methods for Improving Performance of Recursive General Purpose Applications on GPUs.	ISPDC	2008	DBLP DOI BibTeX RDF
1	Aleksandar Ilic, Frederico Pratas, Leonel Sousa	Distributed Web-based Platform for Computer Architecture Simulation.	ISPDC	2008	DBLP DOI BibTeX RDF
1	Svetislav Momcilovic, Leonel Sousa	A Parallel Algorithm for Advanced Video Motion Estimation on Multicore Architectures.	CISIS	2008	DBLP DOI BibTeX RDF
1	Pedro Tomás, João Martins, Leonel Sousa	Towards a Unified Model for the Retina - Static vs Dynamic Integrate and Fire Models.	BIOSIGNALS	2008	DBLP BibTeX RDF
1	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	Merged Computation for Whirlpool Hashing.	DATE	2008	DBLP DOI BibTeX RDF
1	Ricardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	BRAM-LUT Tradeoff on a Polymorphic DES Design.	HiPEAC	2008	DBLP DOI BibTeX RDF
1	Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva	Massive parallel LDPC decoding on GPU.	PPOPP	2008	DBLP DOI BibTeX RDF	parallel processing, graphics processing unit, computer unified device architecture, ldpc, low-density parity-check codes, cuda
1	Leonel Augusto Sousa, Noel E. O'Connor, Marco Mattavelli, Antonio Nunez	Embedded Systems for Portable and Mobile Video Platforms.	EURASIP J. Emb. Sys.	2007	DBLP DOI BibTeX RDF
1	Nuno Roma, Leonel Sousa	Efficient Hybrid DCT-Domain Algorithm for Video Spatial Downscaling.	EURASIP J. Adv. Sig. Proc.	2007	DBLP DOI BibTeX RDF
1	Tiago Dias, Svetislav Momcilovic, Nuno Filipe Valentim Roma, Leonel Sousa	Adaptive Motion Estimation Processor for Autonomous Video Devices.	EURASIP J. Emb. Sys.	2007	DBLP DOI BibTeX RDF
1	Tiago Dias, Nuno Roma, Leonel Sousa, Miguel Ribeiro	Reconfigurable architectures and processors for real-time video motion estimation.	J. Real-Time Image Processing	2007	DBLP DOI BibTeX RDF
1	Shinichi Yamagiwa, Leonel Sousa	Caravela: A Novel Stream-Based Distributed Computing Environment.	IEEE Computer	2007	DBLP DOI BibTeX RDF	Caravela environment, flow-model-based computation, distributed computing, graphics processing units
1	Ricardo Chaves, Leonel Sousa	Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Miguel Ribeiro, Leonel Sousa	A Run-time Reconfigurable Processor for Video Motion Estimation.	FPL	2007	DBLP DOI BibTeX RDF
1	Sérgio F. Martins, Leonel Sousa, João Martins	Additive Logistic Regression Applied to Retina Modelling.	ICIP	2007	DBLP DOI BibTeX RDF
1	Shinichi Yamagiwa, Leonel Sousa, Diogo Antão	Data buffering optimization methods toward a uniform programming interface for gpu-based applications.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	DirectX, general purpose processing, graphics processing unit, OpenGL
1	Shinichi Yamagiwa, Leonel Sousa	Design and implementation of a stream-based distributedcomputing platform using graphics processing units.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	caravela, stream-based computing, GRID, GPU, GPGPU, flow-model
1	Shinichi Yamagiwa, Leonel Sousa, Tomás Brandão	Meta-Pipeline: A New Execution Mechanism for Distributed Pipeline Processing.	ISPDC	2007	DBLP DOI BibTeX RDF
1	Paulo Alexandre Crisóstomo Lopes, José A. Germano, Teresa Mendes de Almeida, Leonel Sousa, Moisés Simões Piedade, Filipe Cardoso, H. A. Ferreira, P. P. Freitas	A New Handheld Biochip-based Microsystem.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Leonel Sousa	Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
1	Leonel Sousa, Moisés Simões Piedade, José A. Germano, Teresa Mendes de Almeida, Paulo Alexandre Crisóstomo Lopes, Filipe Cardoso, Paulo Freitas	Generic Architecture Designed for Biomedical Embedded Systems.	IESS	2007	DBLP DOI BibTeX RDF
1	Oliver Sinnen, Leonel Augusto Sousa, Frode Eika Sandnes	Toward a Realistic Task Scheduling Model.	IEEE Trans. Parallel Distrib. Syst.	2006	DBLP DOI BibTeX RDF	processor involvement, heterogeneous system model, Parallel processing, concurrent programming, scheduling and task partitioning
1	Shinichi Yamagiwa, Leonel Sousa, Kevin Ferreira, Keiichi Aoki, Masaaki Ono, Koichi Wada	Maestro2: Experimental Evaluation of Communication Performance Improvement Techniques in the Link Layer.	Journal of Interconnection Networks	2006	DBLP DOI BibTeX RDF
1	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	Rescheduling for Optimized SHA-1 Calculation.	SAMOS	2006	DBLP DOI BibTeX RDF
1	Tiago Dias, Nuno Roma, Leonel Sousa	Low Power Distance Measurement Unit for Real-Time Hardware Motion Estimators.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Svetislav Momcilovic, Tiago Dias, Nuno Roma, Leonel Sousa	Application Specific Instruction Set Processor for Adaptive Video Motion Estimation.	DSD	2006	DBLP DOI BibTeX RDF
1	Ricardo Chaves, Georgi Kuzmanov, Stamatis Vassiliadis, Leonel Sousa	Reconfigurable memory based AES co-processor.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis	Improving SHA-2 Hardware Implementations.	CHES	2006	DBLP DOI BibTeX RDF	SHA-2 (256, 512), FPGA, Cryptography, Hash functions
1	Rodrigo Piedade, Leonel Sousa	Configurable Embedded Core for Controlling Electro-Mechanical Systems.	ARC	2006	DBLP DOI BibTeX RDF
1	Oliver Sinnen, Leonel Sousa	Communication Contention in Task Scheduling.	IEEE Trans. Parallel Distrib. Syst.	2005	DBLP DOI BibTeX RDF	communication contention, heterogeneous system model, Parallel processing, concurrent programming, scheduling and task partitioning
1	Stamatis Vassiliadis, Leonel Sousa, Georgi Gaydadjiev	The Midlifekicker Microarchitecture Evaluation Metric.	ASAP	2005	DBLP DOI BibTeX RDF	pipeline, microarchitecture, ILP
1	Ricardo Guapo, Leonel Sousa, Shinichi Yamagiwa	On the Implementation and Evaluation of Berkeley Sockets on Maestro2 cluster computing environment.	ISPDC	2005	DBLP DOI BibTeX RDF
1	Nuno Roma, Leonel Sousa	Least squares motion estimation algorithm in the compressed DCT domain for H.26x/MPEG-x video sequences.	AVSS	2005	DBLP DOI BibTeX RDF
1	Oliver Sinnen, Leonel Sousa	List scheduling: extension for contention awareness and evaluation of node priorities for heterogeneous cluster architectures.	Parallel Computing	2004	DBLP DOI BibTeX RDF
1	Oliver Sinnen, Leonel Sousa	On Task Scheduling Accuracy: Evaluation Methodology and Results.	The Journal of Supercomputing	2004	DBLP DOI BibTeX RDF	scheduling accuracy, task scheduling, DAG, scheduling model
1	Michel Leong, Pedro Vasconcelos, Jorge R. Fernandes, Leonel Sousa	A programmable cellular neural network circuit.	SBCCI	2004	DBLP DOI BibTeX RDF	VLSI, cellular neural networks, microelectronics
1	Ricardo Chaves, Leonel Sousa	{2n+1, sn+k, sn-1}: A New RNS Moduli Set Extension.	DSD	2004	DBLP DOI BibTeX RDF
1	Oliver Sinnen, Leonel Sousa	Task Scheduling: Considering the Processor Involvement in Communication.	ISPDC/HeteroPar	2004	DBLP DOI BibTeX RDF	processor involvement, Parallel programming, task scheduling, contention, system models
1	Kevin Ferreira, Shinichi Yamagiwa, Leonel Sousa, Keiichi Aoki, Koichi Wada, Luis Miguel Campos	Distributed Shared Memory System Based on the Maestro2 High Performance Cluster Network.	ISPDC/HeteroPar	2004	DBLP DOI BibTeX RDF	Clusters, Parallel computing, High Performance Computing, Distributed Shared Memory, High Performance Networks
1	Nuno Roma, Leonel Sousa	Fast transcoding architectures for insertion of non-regular shaped objects in the compressed DCT-domain.	Sig. Proc.: Image Comm.	2003	DBLP DOI BibTeX RDF
1	Nuno Roma, Leonel Sousa	Automatic Synthesis of Motion Estimation Processors Based on a New Class of Hardware Architectures.	VLSI Signal Processing	2003	DBLP DOI BibTeX RDF	array architectures, specialized processors, motion estimation, block matching
1	Nuno Roma, Tiago Dias, Leonel Sousa	Customisable Core-Based Architectures for Real-Time Motion Estimation on FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
1	Leonel Sousa, Pedro Tomás, Francisco J. Pelayo, Antonio Martínez, Christian A. Morillas, Samuel F. Romero	An FPL Bioinspired Visual Encoding System to Stimulate Cortical Neurons in Real-Time.	FPL	2003	DBLP DOI BibTeX RDF
1	Ricardo Chaves, Leonel Sousa	RDSP: A RISC DSP based on Residue Number System.	DSD	2003	DBLP DOI BibTeX RDF
1	Nuno Roma, Leonel Sousa	Efficient and configurable full-search block-matching processors.	IEEE Trans. Circuits Syst. Video Techn.	2002	DBLP DOI BibTeX RDF

Publications of Leonel Sousa Leonel Augusto Sousa ( http://dblp.L3S.de/Authors/Leonel_Sousa )