|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 4 occurrences of 4 keywords
|
|
|
|
|
Results
Found 12 publication records. Showing 12 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Katherine Shu-Min Li, Chih-Yun Pai, Liang-Bi Chen |
Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip.  |
IEICE Transactions  |
2011 |
DBLP BibTeX RDF |
|
| 1 | Liang-Bi Chen, Yen-Ling Chen, Ing-Jer Huang |
A Real-Time Power Analysis Platform for Power-Aware Embedded System Development.  |
J. Inf. Sci. Eng.  |
2011 |
DBLP BibTeX RDF |
|
| 1 | Chih-Yun Pai, Ruei-Ting Gu, Bo-Chuan Cheng, Liang-Bi Chen, Katherine Shu-Min Li |
A Unified Interconnects Testing Scheme for 3D Integrated Circuits.  |
Asian Test Symposium  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Xue Zheng, Po-Ping Kan, Liang-Bi Chen, Kai-Yang Hsieh, Bo-Chuan Cheng, Katherine Shu-Min Li |
Fault tolerant application-specific NoC topology synthesis for three-dimensional integrated circuits.  |
SoCC  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Liang-Bi Chen, Jiun-Cheng Ju, Chien-Chou Wang, Ing-Jer Huang |
HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms.  |
IEICE Transactions  |
2010 |
DBLP BibTeX RDF |
|
| 1 | Liang-Bi Chen, Tsung-Yu Ho, Jiun-Cheng Ju, Cheng-Lung Chiang, Chung-Nan Lee, Ing-Jer Huang |
An embedded debugging/performance monitoring engine for a tile-based 3D graphics SoC development.  |
ASP-DAC  |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Liang-Bi Chen, Chi-Tsai Yeh, Hung-Yu Chen, Ing-Jer Huang |
A System-Level Model of Design Space Exploration for a Tile-Based 3D Graphics SoC Refinement.  |
IEICE Transactions  |
2009 |
DBLP BibTeX RDF |
|
| 1 | Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang |
An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics.  |
ASP-DAC  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Liang-Bi Chen, Yung-Chih Liu, Chen-Hung Chen, Chung-Fu Kao, Ing-Jer Huang |
Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor.  |
ASP-DAC  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Ping Young, Chung-Chu Chia, Liang-Bi Chen, Ing-Jer Huang |
NCPA: A Scheduling Algorithm for Multi-cipher and Multi-mode Reconfigurable Cryptosystem.  |
IIH-MSP  |
2008 |
DBLP DOI BibTeX RDF |
multiple cipher, scheduling algorithm, Cryptosystem, operation mode, crypto-coprocessor |
| 1 | Liang-Bi Chen, Ching-Chi Hu, Yen-Ling Chen, Chi-Wei Chu, Ing-Jer Huang |
The AES Design Space Exploration with a Soft IP Generator.  |
IIH-MSP  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Liang-Bi Chen, Ing-Jer Huang, Yuan-Long Jeang |
Design of a Dynamic PCM Selector for Non-deterministic Environment.  |
APCCAS  |
2006 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #12 of 12 (100 per page; Change: )
|
|