| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Fahad Ahmed, Linda Milor |
Analysis and On-Chip Monitoring of Gate Oxide Breakdown in SRAM Cells.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Fahad Ahmed, Mohamed M. Sabry, David Atienza, Linda Milor |
Wearout-aware compiler-directed register assignment for embedded systems. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Bashir, Linda Milor, Dae Hyun Kim, Sung Kyu Lim |
Impact of irregular geometries on low-k dielectric breakdown. |
Microelectronics Reliability |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Fahad Ahmed, Linda Milor |
Via wearout detection with on-chip monitors. |
Microelectronics Journal |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Fahad Ahmed, Linda Milor |
Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Bashir, Linda S. Milor, Dae Hyun Kim, Sung Kyu Lim |
Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown. |
Microelectronics Reliability |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Bashir, Linda S. Milor |
Towards a chip level reliability simulator for copper/low-k backend processes. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Cheng Jia, Linda Milor |
A DLL Design for Testing I/O Setup and Hold Times. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Bashir, Linda Milor |
Modeling Low-k Dielectric Breakdown to Determine Lifetime Requirements. |
IEEE Design & Test of Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Muhammad Bashir, Linda S. Milor |
A methodology to extract failure rates for low-k dielectric breakdown with multiple geometries and in the presence of die-to-die linewidth variation. |
Microelectronics Reliability |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Seyed-Abdollah Aftabjahani, Linda S. Milor |
Timing analysis with compact variation-aware standard cell models. |
Integration |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Seyed-Abdollah Aftabjahani, Linda S. Milor |
Fast Variation-Aware Statistical Dynamic Timing Analysis. |
CSIE |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Seyed-Abdollah Aftabjahani, Linda S. Milor |
Timing Analysis with Compact Variation-Aware Standard Cell Models. |
CSIE |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Fahad Ahmed, Linda S. Milor |
Reliable cache design with detection of gate oxide breakdown using BIST. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Munkang Choi, Linda S. Milor |
Diagnosis of Optical Lithography Faults With Product Test Sets. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng Jia, Linda S. Milor |
A BIST Circuit for DLL Fault Detection. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Seyed-Abdollah Aftabjahani, Linda S. Milor |
Compact Variation-Aware Standard Cell Models for Timing Analysis - Complexity and Accuracy Analysis. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Variation-Aware Timing Models, Standard Cells, Statistical Timing Analysis |
| 1 | Linda Milor, Changsoo Hong |
Backend dielectric breakdown dependence on linewidth and pattern density. |
Microelectronics Reliability |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Changsoo Hong, Linda Milor |
Modeling of the breakdown mechanisms for porous copper/low-k process flows. |
Microelectronics Reliability |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Munkang Choi, Linda S. Milor |
Impact on circuit performance of deterministic within-die variation in nanoscale semiconductor manufacturing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Changsoo Hong, Linda S. Milor, Munkang Choi, Tom Lin |
Study of Area Scaling Effect on Integrated Circuit Reliability Based on Yield Models. |
Microelectronics Reliability |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng Jia, Linda S. Milor |
A BIST Solution for The Test of I/O Speed. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu |
Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu |
Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Mien Li, Linda S. Milor |
Computing Parametric Yield Adaptively Using Local Linear Models. |
DAC |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Bozena Kaminska, Tad A. Kwasniewski, Linda S. Milor, G. Roberts, P. Flahive, Jérôme Wojcik |
Is High Frequency Analog DFT Possible? (PDF / PS) |
VTS |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Linda S. Milor, Alberto L. Sangiovanni-Vincentelli |
Minimizing production test time to detect faults in analog circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Linda Milor, Alberto L. Sangiovanni-Vincentelli |
Optimal Test Set Design for Analog Circuits. |
ICCAD |
1990 |
DBLP BibTeX RDF |
|
| 1 | Linda Milor, Alberto L. Sangiovanni-Vincentelli |
Computing Parametric Yield Accurately and Efficiently. |
ICCAD |
1990 |
DBLP BibTeX RDF |
|
| 1 | Linda S. Milor, V. Visvanathan |
Detection of catastrophic faults in analog integrated circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | V. Visvanathan, Linda S. Milor |
An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation. |
Symposium on Computational Geometry |
1986 |
DBLP DOI BibTeX RDF |
LINPACK |
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