Search results for "Logic"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Karl M. Fant, Scott A. Brandt	NULL Convention Logic/sup TM/: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis.	ASAP	1996	DBLP DOI BibTeX RDF	consistent logic, asynchronous digital circuit synthesis, symbolically complete logic, asynchronous digital circuits, asynchronous circuits, multivalued logic, three value logic, Boolean logic, NULL Convention Logic, four value logic
9	Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser	Logic optimization by output phase assignment in dynamic logic synthesis.	ICCAD	1996	DBLP DOI BibTeX RDF	dynamic logic synthesis, logic duplication, minimum logic duplication penalty, output phase assignment, logic design, heuristic algorithms, optimal algorithms, domino logic, logic optimization, area overhead, logic functions, inverters
8	Torben Braüner	Axioms for classical, intuitionistic, and paraconsistent hybrid logic.	Journal of Logic, Language and Information	2006	DBLP DOI BibTeX RDF	Axiom systems, Modal logic, Paraconsistent logic, Intuitionistic logic, Hybrid logic, Strong negation, Constructive logic
8	José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh	Optimization of combinational and sequential logic circuits for low power using precomputation.	ARVLSI	1995	DBLP DOI BibTeX RDF	sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle
8	Timothy J. McBrayer, Philip A. Wilsey	Process combination to increase event granularity in parallel logic simulation. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	event granularity, VHDL description, parallel processing, logic CAD, circuit analysis computing, logic circuits, logic circuits, symmetric multiprocessors, logic simulation, digital system design, parallel logic simulation, parallel logic simulators
7	Luc De Raedt	Probabilistic Logic Learning - A Tutorial Abstract.	ICLP	2009	DBLP DOI BibTeX RDF	probabilistic logic learning, logic and learning, logic programming, inductive logic programming, statistical relational learning
7	Joshua Sack	Temporal Languages for Epistemic Programs.	Journal of Logic, Language and Information	2008	DBLP DOI BibTeX RDF	Public announcement logic, Games, Temporal logic, Modal logic, Epistemic logic, Dynamic epistemic logic
7	Rostislav Horcík, Petr Cintula	Product L ukasiewicz Logic.	Arch. Math. Log.	2004	DBLP DOI BibTeX RDF	u logic, Takeuti, Titani logic, product MV-algebra, fuzzy logic, logic, many-valued logic, MV-algebra
7	Paul Chang, Brion L. Keller, Sarala Paliwal	Effective parallel processing techniques for the generation of test data for a logic built-in self test system.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	logic built-in self test, complex processor, simulation time, random stimulus generation, signature computation, Pseudo-Random Pattern Generators, serial compression, response data, serial pattern dependency, parallel processing, parallel processing, logic testing, partitioning, built-in self test, integrated circuit testing, automatic test pattern generation, signatures, parallel simulation, microprocessor chips, logic simulation, logic simulation, post processing, logic partitioning, test data
7	Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang	Charge sharing fault analysis and testing for CMOS domino logic circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
7	Noboru Takagi, Kyoichi Nakashima, Masao Mukaidono	A Necessary and Sufficient Condition for Lukasiewicz Logic Functions. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	Lukasiewicz logic functions, Lukasiewicz multiple-valued logic, Lukasiewicz implication, logic design, multivalued logic, negation, multiple-valued functions, multiple-valued logic design
7	Kyeonghoon Koo, Wook Hyun Kwon	Worst-case timing prediction of relay ladder logic by constraint analysis.	RTCSA	1996	DBLP DOI BibTeX RDF	worst-case timing prediction, relay ladder logic, boolean logic equations, logic equations, complexity, logic programming, logic programming, application programs, constraint analysis
7	Mostafa H. Abd-El-Barr, M. N. Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
7	Glenn Jennings	Accurate ternary-valued compiled logic simulation of complex logic networks by OTDD composition.	Annual Simulation Symposium	1995	DBLP DOI BibTeX RDF	circuit diagrams, ternary-valued compiled logic simulation, complex logic networks, OTDD composition, combinational U inaccuracies, reconvergent fanout, Kleenean strong ternary logic, Ordered Ternary Decision Diagram, standard ISCAS 85 benchmarks, performance evaluation, logic CAD, digital simulation, circuit analysis computing, ternary logic, incompletely-specified functions
7	Soumitra Bose, Vishwani D. Agrawal	Sequential logic path delay test generation by symbolic analysis.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	sequential logic path delay test generation, two-vector test sequences, non-scan sequential circuit, multivalued algebras, three-vector test sequences combinational logic, value propagation rule, ISCAS89 benchmarks, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, finite state machines, finite state machines, sequential circuits, encoding, automatic testing, Binary Decision Diagrams, multivalued logic, sequential machines, symbolic analysis, combinational logic, state transitions
7	Alioune Ngom, Corina Reischer, Ivan Stojmenovic	Classification of Functions and Enumeration of Bases of Set Logic under Boolean Compositions. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	set logic bases enumeration, functions classification, Boolean compositions, r-valued set logic, n-tuples, B-maximal sets, set logic, one-place example function, one-place set logic functions, B-Sheffer functions, Boolean functions, Boolean functions, set theory, multivalued logic
7	Takahiro Hozumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Logic Design Using Multiple-Valued EXOR. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued EXOR, sum operation, multiple valued sum of products expression, binary EXOR of MINs expressions, three valued EXOR of MINs expression, three valued two variable functions, multiple valued EXOR of MINs expressions, MAX of MINs, TSUM of MINs expressions, logic design, neural nets, multivalued logic, logic minimization, minimisation of switching nets, neural computing, multiple valued logic design, multiple-valued logic design
7	Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama	Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	multiple-valued arithmetic integrated circuits, dual-rail source-coupled logic, multiple-valued current-mode MOS integrated circuit, high-speed arithmetic systems, multiple-valued source-coupled logic circuit, dual-rail complementary inputs, pipelined multiplier, 54 bit, 200 MHz, 0.8 mum, 1.5 V, CMOS logic circuits, multiplying circuits, multivalued logic circuits, current-mode logic, pipeline arithmetic
7	Seiki Akama	Three-Valued Constructive Logic and Logic Programs. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	three-valued constructive logic, three valued constructive logic, strong negation 3N, N completion, intuitive semantics, N completion semantics, computational complexity, semantics, logic programming, logic programs, ternary logic, model theory, strong negation, negation as failure
7	Shoujue Wang, Xunwei Wu, Hongjuan Feng	The High-Speed Ternary Logic Gates Based on the Multiple beta Transistors. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	high speed ternary logic gates, multiple /spl beta/ transistors, multiple emitter transistor, current gain, linear AND/OR gates, multi valued literal circuits, high speed multi valued logic circuits, multivalued logic circuits, logic gates, ternary logic, transistors
7	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis	Testing combinational iterative logic arrays for realistic faults.	VTS	1995	DBLP DOI BibTeX RDF	combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model
7	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture
7	Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose	Logic synthesis for a single large look-up table. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	single large look-up table, LUT-based field-programmable gate array architectures, simulation time minimisation, compile-code, software simulation, field programmable gate arrays, Boolean function, logic design, logic synthesis, hardware accelerator, programmable logic arrays, table lookup, logic simulation, FPGA architectures, logic functions, on-chip memory, memory constraint
7	Anand Chavan, Shiu-Kai Chin, Shahid Ikram, Jang Dae Kim, Juin-Yeu Zu	Extending VLSI design with higher-order logic. (PDF / PS)	ICCD	1995	DBLP DOI BibTeX RDF	Cambridge Higher-Order Logic theorem-prover, microprogram sequencer, Am2910, VLSI, formal verification, formal verification, logic testing, theorem proving, logic design, logic CAD, VLSI design, higher-order logic, theorem-prover, design environment, instruction-set architecture, VLSI CAD
7	Ashvin Radiya, Robert G. Sargent	A Logic-based Foundation of Discrete Event Modeling and Simulation.	ACM Trans. Model. Comput. Simul.	1994	DBLP DOI BibTeX RDF	logic of events and actions, logic of procedural programming, quantifiers logic, simulation procedure, time flow mechanism, temporal logic, discrete event simulation, logic, model-theoretic semantics, discrete event modeling
7	Hans Jürgen Ohlbach	New Ways for Developing Proof Theories for First-Order Multi Modal Logics.	CSL	1989	DBLP DOI BibTeX RDF	Automated Theorem Proving by Translation and Refutation, Nonclassical Logics, Process Logic, Action Logic, Temporal Logic, Modal Logic, Resolution, Epistemic Logic
6	Yi N. Wang	A Two-Dimensional Hybrid Logic of Subset Spaces.	ICLA	2009	DBLP DOI BibTeX RDF	two-sorted hybrid language, logic of subset spaces, Gentzen system for hybrid logic, hybrid logic
6	Renate A. Schmidt, Dmitry Tishkovsky	On combinations of propositional dynamic logic and doxastic modal logics.	Journal of Logic, Language and Information	2008	DBLP DOI BibTeX RDF	Combinations of modal logics, Doxastic logic, Belief and knowledge, Epistemic logic, Dynamic logic, Reasoning about actions
6	Dexter Kozen, Jerzy Tiuryn	Substructural logic and partial correctness.	ACM Trans. Comput. Log.	2003	DBLP DOI BibTeX RDF	specification, linear logic, Dynamic logic, Hoare logic, sequent calculus, substructural logic, Kleene algebra, Kleene algebra with tests
6	Churn-Jung Liau	An Overview of Hybrid Possibilistic Reasoning.	RSFDGrC	2003	DBLP DOI BibTeX RDF	Qualitative possibility logic, Graded modal logic, Description Logic, Hybrid logic, Possibilistic logic
6	Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama	Fully Source-Coupled Logic Based Multiple-Valued VLSI. (PDF / PS)	ISMVL	2002	DBLP DOI BibTeX RDF	source-coupled logic, differential-pair circuit, current-source control, radix-2 signed-digit adder, multiple-valued logic, current-mode logic
6	Dusan Guller	Procedural Semantics for Fuzzy Disjunctive Programs.	LPAR	2002	DBLP DOI BibTeX RDF	multivalued logic programming, logic in artificial intelligence, fuzzy logic, knowledge representation and reasoning, model theory, disjunctive logic programming
6	Thomas Lukasiewicz	Probabilistic logic programming with conditional constraints.	ACM Trans. Comput. Log.	2001	DBLP DOI BibTeX RDF	conditional constraint, quantitative deduction, computational complexity, logic programming, probability, uncertainty, many-valued logic, probabilistic reasoning, probabilistic logic, probabilistic logic programming
6	Marisa A. Sanchez, Juan Carlos Augusto	Testing an Implementation of a Temporal Logic Language.	SCCC	2000	DBLP DOI BibTeX RDF	temporal logic language, language implementation testing, Temporal Prolog, Hilbert model, formal specification, logic programming, temporal logic, temporal logic, PROLOG, program testing, specification-based testing, inference rules, axioms, program errors
6	Alexander Bolotov, Michael Fisher	A Resolution Method For CTL Branching-Time Temporal Logic. (PDF / PS)	TIME	1997	DBLP DOI BibTeX RDF	resolution method, CTL branching-time temporal logic, clausal resolution method, extended CTL, fairness operators, step resolution, temporal resolution rule, linear-time temporal resolution, temporal logic, completeness, normal form, linear temporal logic, computation tree logic, CTL*
6	Alioune Ngom, Corina Reischer, Dan A. Simovici, Ivan Stojmenovic	Completeness Criteria in Set-Valued Logic Under Compositions with Union and Intersection. (PDF / PS)	ISMVL	1997	DBLP DOI BibTeX RDF	completeness criteria, set-valued logic, Boolean completeness problems, r-valued set logic, logic of functions, n-tuples, set logic circuits, S-complete, U-maximal sets, completeness criterion, U functions, compositions, Boolean functions, Boolean functions, intersection, union
6	Susanto Rahardja, Bogdan J. Falkowski	Family of Fast Mixed Arithmetic Logic Transforms for Multiple-Valued Input Binary Functions. (PDF / PS)	ISMVL	1996	DBLP DOI BibTeX RDF	fast mixed arithmetic logic transforms, multiple-valued input binary functions, transform matrices, mixed arithmetic logic spectra, Boolean functions, transforms, matrix algebra, multivalued logic, multivalued logic circuits, inverse transforms
6	Arun Balakrishnan, Srimat T. Chakradhar	Retiming with logic duplication transformation: theory and an application to partial scan.	VLSI Design	1996	DBLP DOI BibTeX RDF	logic duplication transformation, partial scan application, RLD configurations, RLD transformation, testability metrics, scan flip-flops, sequential circuit design, linear programming, timing, integer programming, logic design, sequential circuits, logic CAD, polynomial time algorithm, integer linear program, flip-flops, retiming, integrated circuit design, circuit CAD, integrated logic circuits, objective function
6	S. Sundaram, Lalit M. Patnaik	Distributed logic simulation: time-first evaluation vs. event driven algorithms.	VLSI Design	1996	DBLP DOI BibTeX RDF	distributed logic simulation, time-first evaluation algorithm, event driven algorithm, digital circuit simulation, distributed simulation algorithms, parallel algorithms, parallel processing, VLSI, logic CAD, circuit analysis computing, integrated logic circuits, VLSI circuits, parallel logic simulation
6	Dhiraj K. Pradhan, Debjyoti Paul, Mitrajit Chatterjee	VERILAT: verification using logic augmentation and transformations.	ICCAD	1996	DBLP DOI BibTeX RDF	VERILAT, formal logic verification, implication-based methods, logic augmentation, logic transformations, logic testing
6	Mallika De, Bhabani P. Sinha	Testing of a parallel ternary multiplier using I/sup 2/L logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	integrated injection logic, parallel ternary multiplier, I/sup 2/L logic, multivalued I/sup 2/L circuits, input balanced ternary full adder, precarry generator, multivalued current inputs, multivalued current outputs, generated test sets, skew fault, fault diagnosis, logic testing, design for testability, logic design, digital arithmetic, fault location, stuck-at fault, generalized model, adders, adder, multiplying circuits, multivalued logic circuits, test sets, parallel multiplier
6	S. Nandi, Parimal Pal Chaudhuri	Theory and applications of cellular automata for synthesis of easily testable combinational logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph
6	Fadi Y. Busaba, Parag K. Lala	A graph coloring based approach for self-checking logic circuit design.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	logic circuit design, bidirectional error, residue weights assignments, output lines, errors identification, graph theory, logic testing, integrated circuit testing, logic design, error detection, error detection, automatic testing, graph coloring, fault location, integrated logic circuits, graph colouring, self-checking, residue codes, single stuck-at fault
6	Debesh K. Das, Bhargab B. Bhattacharya	Testable design of non-scan sequential circuits using extra logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
6	Kaoru Hirota	Fuzzy logic and its hardware implementation.	ANNES	1995	DBLP DOI BibTeX RDF	fuzzy logic circuit, fuzzy inference chips, fuzzy flip flops, fuzzy logic, fuzzy logic, fuzzy systems, flip-flops, logic circuits, hardware implementation
6	Kaushik De, John A. Chandy, Sumit Roy, Steven Parkes, Prithviraj Banerjee	Parallel algorithms for logic synthesis using the MIS approach. (PDF / PS)	IPPS	1995	DBLP DOI BibTeX RDF	combinational logic synthesis, VLSI system design, ProperMIS, portable parallel algorithm, parallel algorithms, parallel algorithms, parallel architectures, logic design, combinational circuits, logic synthesis, logic CAD
6	Yutaka Hata, Naotake Kamiura, Kazuharu Yamato	On Input Permutation Technique for Multiple-Valued Logic Synthesis. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	input permutation technique, multiple-valued logic synthesis, multiple valued sum of products expressions, TSUM, minimal sum of products expressions, permuted logic values, randomly generated functions, input permutation, output permutation, minimization times, window literals, sum of products expressions, set literals, logic design, set theory, multivalued logic
6	A. K. Jain, Mostafa H. Abd-El-Barr, R. J. Bolton	Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function
6	U. K. Bhattacharyya, I. Sen Gupta, S. Shyama Nath, P. Dutta	PLA based synthesis and testing of hazard free logic.	VLSI Design	1995	DBLP DOI BibTeX RDF	PLA based synthesis, hazard free logic, multilevel network, supergate partitioning, multi-output circuits, testing, logic testing, design for testability, combinational circuits, logic CAD, testability, programmable logic arrays, logic partitioning, combinational networks, hazards and race conditions
6	Matthias Baaz, Alexander Leitsch, Richard Zach	Incompleteness of a First-Order Gödel Logic and Some Temporal Logics of Programs.	CSL	1995	DBLP DOI BibTeX RDF	temporal logic, many-valued logic, intermediate logic
6	Joel Grodstein, Eric Lehman, Heather Harkness, Bill Grundmann, Yosinatori Watanabe	A delay model for logic synthesis of continuously-sized networks.	ICCAD	1995	DBLP DOI BibTeX RDF	algebraic factorings, computational simplicity, continuous device sizing, continuously-sized networks, electrical noise, library cell, mapped network, logic design, logic synthesis, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, delay model, power constraints
6	Sasan Iman, Massoud Pedram	Two-level logic minimization for low power.	ICCAD	1995	DBLP DOI BibTeX RDF	Power Prime Implicants, low power two-level logic minimization, minimum covering problem, minimum power solution, static CMOS circuits, logic design, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, circuit optimisation, minimisation of switching nets
6	Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz	LOT: logic optimization with testability-new transformations using recursive learning.	ICCAD	1995	DBLP DOI BibTeX RDF	EX-OR gates, logic optimization with testability, multi-level logic circuits, tstfx, logic design, combinational circuits, logic CAD, gate level, random-pattern testability, recursive learning
6	Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia	Fast discrete function evaluation using decision diagrams.	ICCAD	1995	DBLP DOI BibTeX RDF	address lookups, cycle-based logic simulation, decision-diagram based function evaluation, fast discrete function evaluation, latch ports, orders-of-magnitude potential speedup, output ports, logic design, memory hierarchy, logic CAD, decision theory, circuit analysis computing, memory bandwidth, table lookup, digital circuits, logic simulators, logic function, function evaluation, multi-valued decision diagrams
6	Tadeusz Luba	Decomposition of Multiple-Valued Functions. (PDF / PS)	ISMVL	1995	DBLP DOI BibTeX RDF	silicon space, PLA implementations, information storing systems, information systems, logic design, decomposition, logic synthesis, programmable logic arrays, multivalued logic, logic circuits, data bases, multiple-valued functions
6	Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal	An efficient automatic test generation system for path delay faults in combinational circuits.	VLSI Design	1995	DBLP DOI BibTeX RDF	automatic test generation system, test pattern generation system, nonrobust tests, nine-value logic system, multiple backtrace procedure, path selection method, logic testing, delays, integrated circuit testing, fault detection, ATPG, combinational circuits, combinational circuits, automatic testing, fault location, multivalued logic, logic circuits, integrated logic circuits, path delay faults, robust tests
6	Steven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng	Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability.	VLSI Design	1995	DBLP DOI BibTeX RDF	stuck-at fault testability, robust path delay fault testability, multilevel logic, hazard-free logic, synthesis for testability method, multi-level circuit, minimization algorithms, logic testing, delays, redundancy, design for testability, logic design, combinational circuits, asynchronous circuits, asynchronous circuits, multivalued logic circuits, minimisation of switching nets, area overhead, hazards and race conditions
6	Alessandro Bogliolo, Maurizio Damiani	Synthesis of combinational circuits with special fault-handling capabilitie.	VTS	1995	DBLP DOI BibTeX RDF	combinational circuit synthesis, fault-handling capabilities, internal faults, multilevel logic optimization process, logic testing, redundancy, redundancy, design for testability, logic design, combinational circuits, logic CAD, multivalued logic, circuit optimisation, self-checking circuits, circuit reliability, fault-tolerant circuits
6	Thomas J. Weigert, Jeffrey J. P. Tsai	A Computationally Tractable Nonmonotonic Logic.	IEEE Trans. Knowl. Data Eng.	1994	DBLP DOI BibTeX RDF	computationally tractable nonmonotonic logic, nonmonotonic reasoning procedures, proof theoretically, semantic characteristics, Herbrand subset, knowledge representation, logic programming, logic programming, reasoning, nonmonotonic reasoning, incomplete information, formal logic, first-order predicate logic
6	Shih-Yuang Su, Cheng-Wen Wu	Testing Iterative Logic Arrays for Sequential Faults with a Constant Number of Patterns.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	sequential faults, ILA, M-testability, constant-length test sequence, pipelined array multiplier, sequential fault testing, logic testing, logic testing, sequential circuits, test pattern generation, logic arrays, combinatorial circuits, test vectors, C-testability, iterative logic arrays, iterative logic array
6	Uday S. Reddy	A Typed Foundation for Directional Logic Programming.	ELP	1992	DBLP DOI BibTeX RDF	Directionality, types, linear logic, sequent calculus, modes, concurrent logic programming, Curry-Howard isomorphism, logic variables
6	Gerald M. Karam, Raymond J. A. Buhr	Temporal Logic-Based Deadlock Analysis For Ada.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	temporal logic-based specification language, deadlock analyzer, Timebench, concurrent system-design environment, COL, linear-time temporal logic, formal basis, axiomatic reasoning, deadlock analysis tool, reasoning power, Ada designs, systemwide deadlock-free, deadlock algorithm, finite systems, worst-case computational complexity, gas station, layered communications system, computational complexity, Ada, logic programming, temporal logic, Prolog, specification language, specification languages, inference mechanisms, system recovery, theorem prover, readers, dining philosophers, writers
6	Phan Minh Dung	On the strong completion of logic programs.	ALP	1990	DBLP DOI BibTeX RDF	predicate completion, two-valued logic, Logic programming, negation, three-valued logic, stable models, circumscription, well-founded models
6	Françoise Debart, Patrice Enjalbert, Madeleine Lescot	Multi-Modal Logic Programming using Equational and Order-Sorted Logic.	ALP	1990	DBLP DOI BibTeX RDF	Order-sorted Logic, Equationnal Methods, E-Resolution, Logic Programming, Modal Logic, Unification
6	Michael Kifer, Eliezer L. Lozinskii	SYGRAF: Implementing Logic Programs in a Database Style.	IEEE Trans. Software Eng.	1988	DBLP DOI BibTeX RDF	SYGRAF, Horn logic programs, function symbols, parallel programming, logic programming, logic programming, query optimization, database theory, deductive databases, programming theory, formal logic, bottom-up evaluation
6	Tsutomu Sasao, Kozo Kinoshita	Cascade Realization of 3-Input 3-Output Conservative Logic Circuits.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	universality of logic elements, Cascade realization, conservative logic element (CLE), logic primitives, magnetic bubble logic, minimum circuit, three-valued logic
6	Alexander Iosupovicz	Adaptive Universal Fault-Tolerant Logic Networks.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	dynamic error correction, fault-tolerant logic, tree arrays, universal logic modules, programmable logic, cellular logic, Adaptive logic
5	Harold Boley, Michael Kifer	A Guide to the Basic Logic Dialect for Rule Interchange on the Web.	IEEE Trans. Knowl. Data Eng.	2010	DBLP DOI BibTeX RDF	F-logic, XML, Logic programming, equality, deduction, IRI, mathematical logic, RIF, Horn logic
5	Daniele Genito, Giangiacomo Gerla, Alessandro Vignes	Meta-logic programming for a synonymy logic.	Soft Comput.	2010	DBLP DOI BibTeX RDF	Synonymy logic, Fuzzy logic, Logic programming, Translation
5	Derek Dreyer, Georg Neis, Andreas Rossberg, Lars Birkedal	A relational modal logic for higher-order stateful ADTs.	POPL	2010	DBLP DOI BibTeX RDF	local state, plotkin-abadi logic, modal logic, abstract data types, separation logic, step-indexed logical relations
5	GuoJun Wang, QiaoLin Duan	Theory of (n) truth degrees of formulas in modal logic and a consistency theorem.	Science in China Series F: Information Sciences	2009	DBLP DOI BibTeX RDF	(n) truth degrees, consistency theorem, (n) modality similarity degrees, (n) modality logic metric space, temporal logic, modal logic, approximate reasoning
5	Wesley H. Holliday	Dynamic Testimonial Logic.	LORI	2009	DBLP DOI BibTeX RDF	testimony, trust, modal logic, belief revision, dynamic logic
5	Rafael Caballero, Mario Rodríguez-Artalejo, Carlos A. Romero-Díaz	Qualified Computations in Functional Logic Programming.	ICLP	2009	DBLP DOI BibTeX RDF	Constraints, Program Transformation, Rewriting Logic, Functional Logic Programming, Qualification
5	Esko Turunen	A Para Consistent Fuzzy Logic.	ICLA	2009	DBLP DOI BibTeX RDF	Mathematical fuzzy logic, para consistent sentential logic, MV-algebra
5	Patrick Girard, Jeremy Seligman	An Analytic Logic of Aggregation.	ICLA	2009	DBLP DOI BibTeX RDF	preference logic, lexicographic aggregation, hybrid modal logic, analytic proof theory, sequent calculus
5	Jürgen Landes, Jeff B. Paris, Alena Vencovská	Instantial Relevance in Polyadic Inductive Logic.	ICLA	2009	DBLP DOI BibTeX RDF	Instantial Relevance, Spectrum Exchangeability, Uncertain Reasoning, Probability Logic, Inductive Logic
5	Cédric Dégremont, Nina Gierasimczuk	Can Doxastic Agents Learn? On the Temporal Structure of Learning.	LORI	2009	DBLP DOI BibTeX RDF	Formal learning theory, doxastic epistemic logic, epistemic update, temporal logic, belief revision, dynamic epistemic logic
5	Susana Muñoz-Hernández, Victor Pablos Ceruelo, Hannes Strass	RFuzzy: An Expressive Simple Fuzzy Compiler.	IWANN	2009	DBLP DOI BibTeX RDF	Implementation tool, Multi-adjoint logic, Logic Programming Implementation, Fuzzy Logic Application, Fuzzy Logic, Fuzzy reasoning
5	Giorgi Japaridze	Many Concepts and Two Logics of Algorithmic Reduction.	Studia Logica	2009	DBLP DOI BibTeX RDF	Affine logic, Interactivecomputation, Linear logic, Game semantics, Intuitionistic logic, Computability logic
5	Oscar Montiel, Oscar Castillo, Patricia Melin, Roberto Sepúlveda	Mediative fuzzy logic: a new approach for contradictory knowledge management.	Soft Comput.	2008	DBLP DOI BibTeX RDF	Mediative fuzzy logic, Fuzzy logic, Paraconsistent logic
5	Fabrizio Riguzzi	ALLPAD: approximate learning of logic programs with annotated disjunctions.	Machine Learning	2008	DBLP DOI BibTeX RDF	Logic programs with annotated disjunctions, Inductive logic programming, Statistical relational learning, Probabilistic logic programming
5	Bernhard Heinemann	A Hybrid Logic for Reasoning about Knowledge and Topology.	Journal of Logic, Language and Information	2008	DBLP DOI BibTeX RDF	The logic of knowledge, Nominalstructure for subset spaces, Algebras of sets, Hybrid logic, Topological reasoning
5	Pablo F. Castro, T. S. E. Maibaum	A Tableaux System for Deontic Action Logic.	DEON	2008	DBLP DOI BibTeX RDF	Deontic Action Logic, Tableaux Systems, Fault-tolerance, Modal Logic, Software Specification
5	Sergei N. Artëmov, Elena Nogina	Topological Semantics of Justification Logic.	CSR	2008	DBLP DOI BibTeX RDF	Justification Logic, Logic of Proofs, topological semantics, Tarski, modal logic
5	Gergely Lukácsy, Péter Szeredi, Balázs Kádár	Prolog Based Description Logic Reasoning.	ICLP	2008	DBLP DOI BibTeX RDF	logic programming, description logic, resolution, large data sets
5	Fabrizio Riguzzi	Inference with Logic Programs with Annotated Disjunctions under the Well Founded Semantics.	ICLP	2008	DBLP DOI BibTeX RDF	Topics Probabilistic Logic Programming, Logic Programs with Annotated Disjunctions, Well Founded Semantics, SLG resolution
5	Tatiana Yavorskaya	Interacting Explicit Evidence Systems.	Theory Comput. Syst.	2008	DBLP DOI BibTeX RDF	Justification logic, Explicit evidence, Logic of proofs, Epistemic logic, Multi-modal logic
5	Dov M. Gabbay, John Woods	Resource-origins of Nonmonotonicity.	Studia Logica	2008	DBLP DOI BibTeX RDF	fallacies, fuzzy logic, psychologism, Resource, probabilistic logic, nonmonotonic logic, defeasible logic
5	H. Kushida, M. Okada	A proof-theoretic study of the correspondence of hybrid logic and classical logic.	Journal of Logic, Language and Information	2007	DBLP DOI BibTeX RDF	Proof theory, Hybrid logic, Classical logic
5	Leon Horsten, Philip Welch	The Undecidability of Propositional Adaptive Logic.	Synthese	2007	DBLP DOI BibTeX RDF	Dynamic logic, Undecidability, Paraconsistent logic, Adaptive logic
5	Vladimir V. Rybakov	Until-Since Temporal Logic Based on Parallel Time with Common Past. Deciding Algorithms.	LFCS	2007	DBLP DOI BibTeX RDF	admissible inference rules, Temporal logic, linear temporal logic, branching time logic
5	André Platzer	A Temporal Dynamic Logic for Verifying Hybrid System Invariants.	LFCS	2007	DBLP DOI BibTeX RDF	logic for hybrid systems, deductive verification of embedded systems, temporal logic, dynamic logic, sequent calculus
5	Pablo F. Castro, T. S. E. Maibaum	A Complete and Compact Propositional Deontic Logic.	ICTAC	2007	DBLP DOI BibTeX RDF	Fault tolerance, Temporal Logic, Modal Logic, Software Specification, Deontic Logic
5	Paul Tarau, Brenda Luderman	A Logic Programming Framework for Combinational Circuit Synthesis.	ICLP	2007	DBLP DOI BibTeX RDF	logic programming and circuit design, combinatorial object generation, exact combinational circuit synthesis, universal boolean logic libraries, symbolic rewriting, minimal transistor-count circuit synthesis
5	Scott C. Smith	Design of a logic element for implementing an asynchronous FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	NULL convention logic (NCL), asynchronous logic design, field programmable gate array (FPGA), reconfigurable logic, delay-insensitive circuits
5	Thomas Popp, Mario Kirschbaum, Thomas Zefferer, Stefan Mangard	Evaluation of the Masked Logic Style MDPL on a Prototype Chip.	CHES	2007	DBLP DOI BibTeX RDF	DPA-Resistant Logic Styles, Masked Logic, Dual-Rail Precharge Logic, Early Propagation Effect, Improved MDPL, Prototype Chip
5	Germano Resconi, Boris Kovalerchuk	Explanatory Model for the Break of Logic Equivalence by Irrational Agents in Elkan's Paradox.	EUROCAST	2007	DBLP DOI BibTeX RDF	explanatory model, logic equivalence, irrational agent, inconsistent agent, Fuzzy logic, classical logic, paradox, rational agent
5	Radim Belohlávek, Vilém Vychodil	Fuzzy Horn logic I.	Arch. Math. Log.	2006	DBLP DOI BibTeX RDF	Degree of provability, Fuzzy logic, Implication, Equational logic, Horn logic
5	Michael J. C. Gordon, Warren A. Hunt Jr., Matt Kaufmann, James Reynolds	An embedding of the ACL2 logic in HOL.	ACL2	2006	DBLP DOI BibTeX RDF	HOL4, proof oracle, sound translation, verification, formal methods, logic, first-order logic, higher-order logic, ACL2, HOL
5	Ramon Jansana	Selfextensional Logics with a Conjunction.	Studia Logica	2006	DBLP DOI BibTeX RDF	selfextensional logic, Fregan logic, generalized matrix, full generalized model, fully adequate Gentzen system, algebraic logic, algebraizable logic