Search results for "Logic Test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Sreejit Chakravarty	Improving Logic Test Quality of Microprocessors.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Tobias Strauch	Single Cycle Access Structure for Logic Test.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Garrett Kent Kaminski, Paul Ammann	Reducing logic test set size while preserving fault detection.	Softw. Test., Verif. Reliab.	2011	DBLP DOI BibTeX RDF
1	Dongsoo Lee, Kaushik Roy	Viterbi-Based Efficient Test Data Compression.	European Test Symposium	2011	DBLP DOI BibTeX RDF	On-Chip Decompressor, Scalability, Logic Test, Test Data Compression, Low-Power Test
1	Heinrich Theodor Vierhaus, René Kothe	Embedded Diagnostic Logic Test Exploiting Regularity.	DSD	2008	DBLP DOI BibTeX RDF
1	Yu Huang 0005, Ruifeng Guo, Wu-Tung Cheng, James Chien-Mo Li	Survey of Scan Chain Diagnosis.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu	Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Christian Galke, U. Gätzschmann, Heinrich Theodor Vierhaus	Scan-Based SoC Test Using Space / Time Pattern Compaction Schemes.	DSD	2006	DBLP DOI BibTeX RDF
1	Abdul Wahid Hakmi, Hans-Joachim Wunderlich, Valentin Gherman, Michael Garbers, Jürgen Schlöffel	Implementing a Scheme for External Deterministic Self-Test.	VTS	2005	DBLP DOI BibTeX RDF	Deterministic self-test, external BIST, test data compression, test resource partitioning
1	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, Tsutomu Hondo	CMOS Floating Gate Defect Detection Using I DDQ Test with DC Power Supply.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
1	Kenneth D. Wagner	Robust Scan-Based Logic Test in VDSM Technologies.	IEEE Computer	1999	DBLP DOI BibTeX RDF
1	Lee Melatti, Barry Blancha	Testing Methodology for FireWire.	IEEE Design & Test of Computers	1999	DBLP DOI BibTeX RDF
1	Dilip K. Bhavsar, Ugonna Echeruo, David R. Akeson, William J. Bowhill	A highly testable and diagnosable fabrication process test chip.	ITC	1998	DBLP DOI BibTeX RDF
1	Prab Varma, Sandeep Bhatia	A structured test re-use methodology for core-based system chips.	ITC	1998	DBLP DOI BibTeX RDF
1	Karim Arabi, Bozena Kaminska, Mohamad Sawan	On chip testing data converters using static parameters.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Robert Wu, Jerry Gerner, Richard Wheelus, Kevin Lew	Testing Logic-Intensive Memory ICs on Memory Testers.	IEEE Design & Test of Computers	1997	DBLP DOI BibTeX RDF
1	Niranjan L. Cooray, Edward W. Czeck	Guaranteed fault detection sequences for single transition faults in finite state machine models using concurrent fault simulation.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	sequential logic test generation, finite state machine testing, transition fault, distinguishing sequences
1	Karim Arabi, Bozena Kaminska, Janusz Rzeszut	BIST for D/A and A/D Converters.	IEEE Design & Test of Computers	1996	DBLP DOI BibTeX RDF
1	Eiji Harada, Janak H. Patel	Overhead reduction techniques for hierarchical fault simulation.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	overhead reduction techniques, hierarchical fault simulation, simulation overhead, concurrent method, multi-list-traversal method, one-pass fault simulation strategy, characteristic vectors, contiguous concurrent machines, ISCAS benchmark circuits, fault ordering, logic test sequences, fault diagnosis, logic testing, combinational circuits, logic CAD, digital simulation, circuit analysis computing, concurrent engineering, multivalued logic circuits, ULSI, ULSI
1	Chun-Hung Chen, Jacob A. Abraham	Generation and evaluation of current and logic tests for switch-level sequential circuits.	J. Electronic Testing	1992	DBLP DOI BibTeX RDF	logic tests, test generation, Current tests, I DDQ
1	Chun-Hung Chen, Jacob A. Abraham	High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms.	ITC	1991	DBLP DOI BibTeX RDF
1	Fevzi Belli, Ismael Camara, Alfred Schmidt	A Built-in Test Language for PROLOG to Validate Knowledge-Based Systems.	IEA/AIE (Vol. 2)	1990	DBLP DOI BibTeX RDF	Prolog
1	Kwang-Ting Cheng, Vishwani D. Agrawal	An economical scan design for sequential logic test generation.	FTCS	1989	DBLP DOI BibTeX RDF
1	Donald T. Tang, Chin-Long Chen	Logic Test Pattern Generation Using Linear Codes.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF
1	R. N. Powell	IBM's VLSI Logic Test System.	ITC	1981	DBLP BibTeX RDF
1	Frank B. Cole	Automatic generation of functional logic test programs through simulation.	DAC	1970	DBLP DOI BibTeX RDF
1	Manuel Correia, Richard L. Daubenmire	The use of engineering documentation in support of a high density logic test system.	DAC	1968	DBLP DOI BibTeX RDF