Search results for "Low Power BIST"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Ioannis Voyiatzis	Embedding test patterns into Low-Power BIST sequences.	IOLTS	2007	DBLP DOI BibTeX RDF	Test set embedding, Gray sequences, Low power sequences, Built-In Self Test
2	Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira, Salvador Manich, Rosa Rodríguez-Montañés, Joan Figueras	RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST.	ITC	2002	DBLP DOI BibTeX RDF
2	Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Paulo J. Teixeira, Marcelino B. Santos	Low Power BIST by Filtering Non-Detecting Vectors.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	low power BIST, low energy consumption, LFSR, gated clock
2	Dimitris Bakalis, Dimitris Nikolos, George Alexiou, Emmanouil Kalligeros, Haridimos T. Vergos	Low Power BIST for Wallace Tree-Based Fast Multipliers.	ISQED	2000	DBLP DOI BibTeX RDF	Testing, Low Power, BIST, Multipliers, Wallace Trees
2	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
2	Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Effective Low Power BIST for Datapaths.	DATE	2000	DBLP DOI BibTeX RDF
2	Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante	Optimal Vector Selection for Low Power BIST. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	Test, Low-Power, BIST
1	Youbean Kim, Jaewon Jang, Hyunwook Son, Sungho Kang	Pattern Mapping Method for Low Power BIST Based on Transition Freezing Method.	IEICE Transactions	2010	DBLP BibTeX RDF
1	N.-C. Lai, S.-J. Wang, Y.-H. Fu	Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Ji Li, Yinhe Han, Xiaowei Li	Deterministic and low power BIST based on scan slice overlapping.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Jinkyu Lee, Nur A. Touba	Low Power BIST Based on Scan Partitioning.	DFT	2005	DBLP DOI BibTeX RDF
1	Youbean Kim, Myung-Hoon Yang, Yong Lee 0002, Sungho Kang	A New Low Power Test Pattern Generator using a Transition Monitoring Window based on BIST Architecture.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Ling Zhang, Jishun Kuang	A New BIST Solution for System-on-Chip.	PRDC	2005	DBLP DOI BibTeX RDF
1	Maciej Bellos, Dimitris Bakalis, Dimitris Nikolos	Scan Cell Ordering for Low Power BIST.	ISVLSI	2004	DBLP DOI BibTeX RDF
1	Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu	Low Power BIST with Smoother and Scan-Chain Reorder .	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Ehsan Atoofian, Zainalabedin Navabi	A Low Power BIST Architecture for FPGA Look-Up Table Testing.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Xiaoding Chen, Michael S. Hsiao	Energy-Efficient Logic BIST Based on State Correlation Analysis.	VTS	2003	DBLP DOI BibTeX RDF
1	Dimitris Bakalis, Emmanouil Kalligeros, Dimitris Nikolos, Haridimos T. Vergos, George Alexiou	On the design of low power BIST for multipliers with Booth encoding and Wallace tree summation.	Journal of Systems Architecture	2002	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich	High Defect Coverage with Low-Power Test Sequences in a BIST Environment.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich	A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.	VTS	2001	DBLP DOI BibTeX RDF
1	Xiaodong Zhang, Kaushik Roy	Peak Power Reduction in Low Power BIST.	ISQED	2000	DBLP DOI BibTeX RDF	BIST Synthesis, Weighted Random Pattern Generator, Testing, Low Power
1	Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch	Low power BIST design by hypergraph partitioning: methodology and architectures.	ITC	2000	DBLP DOI BibTeX RDF
1	Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	Low Power BIST via Non-Linear Hybrid Cellular Automata.	VTS	2000	DBLP DOI BibTeX RDF
1	Xiaodong Zhang, Kaushik Roy	Power Reduction in Test-Per-Scan BIST.	IOLTW	2000	DBLP DOI BibTeX RDF	Test-per-scan, Low Power BIST, Testing, Low Power, BIST, Weighted Random Pattern
1	Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian	Low Power/Energy BIST Scheme for Datapaths.	VTS	2000	DBLP DOI BibTeX RDF
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	BIST Design, Test, Low-power Design, Energy Consumption
1	Xiaodong Zhang, Kaushik Roy	Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. (PDF / PS)	DFT	1999	DBLP DOI BibTeX RDF	BIST Synthesis, Weighted Random Pattern Generator, Low Power BIST, Testing, Low Power, Cellular Automata, Peak Power