Search results for "Low power VLSI design"

Found 15 publication records. Showing 15 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Anand Raghunathan, Niraj K. Jha	An iterative improvement algorithm for low power data path synthesis.	ICCAD	1995	DBLP DOI BibTeX RDF	Low power VLSI design, Power consumption, Behavioral synthesis
1	Weihuang Wang, Euncheol Kim, Kiran K. Gunnam, Gwan S. Choi	Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Weihuang Wang, Gwan S. Choi, Kiran K. Gunnam	Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama	Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Jongsun Park, Kaushik Roy	A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	Low power VLSI design, Low computational complexity, Discrete cosine transform
1	Himanshu Thapliyal, A. Prasad Vinod	Designing Efficient Online Testable Reversible Adders With New Reversible Gate.	ISCAS	2007	DBLP DOI BibTeX RDF
1	W. H. Muthumala, Masanori Hariyama, Michitaka Kameyama	GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Myungchul Yoon	Sequence-switch coding for low-power data transmission.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Alan J. Drake, Kevin J. Nowka, Richard B. Brown	Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Bill Pontikakis, Mohamed Nekili	A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.	ISCAS	2002	DBLP DOI BibTeX RDF
1	W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi	Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design.	ISLPED	2001	DBLP DOI BibTeX RDF
1	Zhong-Li He, Chi-Ying Tsui, Kai-Keung Chan, Ming L. Liou	Low-power VLSI design for motion estimation using adaptive pixel truncation.	IEEE Trans. Circuits Syst. Video Techn.	2000	DBLP DOI BibTeX RDF
1	Nicola Dragone, Roberto Zafalon, Carlo Guardiani, Cristina Silvano	Power invariant vector compaction based on bit clustering and temporal partitioning.	ISLPED	1998	DBLP DOI BibTeX RDF	low power VLSI design, vector compaction, Markov chains, power estimation
1	Mircea R. Stan, Wayne P. Burleson	Bus-invert coding for low-power I/O.	IEEE Trans. VLSI Syst.	1995	DBLP DOI BibTeX RDF
1	Kaushik Roy, Abhijit Chatterjee	Guest Editors' Introduction: Low-Power VLSI Design.	IEEE Design & Test of Computers	1994	DBLP BibTeX RDF