Search results for "Low power multiplier"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
2	Chua-Chin Wang, Gang-Neng Sung	Low-Power Multiplier Design Using a Bypassing Technique.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Timing control, Partial product, Bypassing
2	Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, Chia-Jen Sheu	Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.	APCCAS	2006	DBLP DOI BibTeX RDF
2	Ko-Chi Kuo, Chi-Wen Chou	Low Power Multiplier with Bypassing and Tree Strucuture.	APCCAS	2006	DBLP DOI BibTeX RDF
1	S. Saravanan, M. Madheswaran	Design and Analysis of a Spurious Switching Suppression Technique Equipped Low Power Multiplier with Hybrid Encoding Scheme	CoRR	2010	DBLP BibTeX RDF
1	S. Saravanan, M. Madheswaran	Design and analysis of a hybrid encoded low power multiplier with reduced transition activity technique.	ICWET	2010	DBLP DOI BibTeX RDF
1	Meng-Lin Hsia, Oscal T.-C. Chen	Low-power Multiplier Optimized by Partial-Product Summation and Adder Cells.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Jin-Tai Yan, Zhi-Wei Chen	Low-power multiplier design with row and column bypassing.	SoCC	2009	DBLP DOI BibTeX RDF
1	Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi	Sign Bit Reduction Encoding For Low Power Applications.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Low power multiplier, Signed multiplier, Sign extension, FIR filter, Power reduction, Energy reduction, Bus encoding
1	Kuan-Hung Chen, Yuan-Sun Chu	A Low-Power Multiplier With the Spurious Power Suppression Technique.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Kuan-Hung Chen, Yuan-Sun Chu, Yu-Min Chen, Jiun-In Guo	A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression Technique.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rahul M. Badghare, Rajendra M. Patrikar	FPGA Implementation of Low Power Parallel Multiplier.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Mohammad Riazati, Ashkan Sobhani, M. Mottaghi-Dastjerdi, Ali Afzali-Kusha, Ali Khaki-Firooz	Low-power multiplier with static decision for input manipulation.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Ko-Chi Kuo, Chi-Wen Chou	A Low-Power Multiplier with Bypassing Logic and Operand Decomposition.	IMECS	2006	DBLP BibTeX RDF
1	Chip-Hong Chang, Ravi Kumar Satzoda, Swaminathan Sekar	A novel multiplexer based truncated array multiplier.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang	Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization.	VLSI Signal Processing	2004	DBLP DOI BibTeX RDF	low-power multiplier, coefficient optimization, power weight factor, power modeling
1	Masayoshi Fujino, Vasily G. Moshnyaga	Dynamic operand transformation for low-power multiplier-accumulator design.	ISCAS	2003	DBLP DOI BibTeX RDF
1	V. A. Bartlett, Andrew G. Dempster	Using carry-save adders in low-power multiplier blocks.	ISCAS	2001	DBLP DOI BibTeX RDF
1	Amr G. Wassal, M. Anwarul Hasan, Mohamed I. Elmasry	Low-Power Design of Finite Field Multipliers for Wireless Applications.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	architecture, low power, finite fields, multiplier
1	Gerald E. Sobelman, Donovan L. Raatz	Low-Power Multiplier Design Using Delayed Evaluation.	ISCAS	1995	DBLP BibTeX RDF