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Found 7 publication records. Showing 7 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Lucas Brusamarello, Gilson I. Wirth, Philippe Roussel, Miguel Miranda |
Fast and accurate statistical characterization of standard cell libraries.  |
Microelectronics Reliability  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Miguel Miranda, Philippe Roussel, Lucas Brusamarello, Gilson I. Wirth |
Statistical characterization of standard cells using design of experiments with response surface modeling. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Lucas Brusamarello, Gilson I. Wirth, Roberto da Silva |
Statistical RTS model for digital circuits. |
Microelectronics Reliability |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis |
Probabilistic Approach for Yield Analysis of Dynamic Logic Circuits. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo Augusto da Luz Reis |
Técnicas probabilísticas para análise de yield em nível elétrico usando propagação de erros e derivadas numéricas. |
RITA |
2007 |
DBLP BibTeX RDF |
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| 1 | Lucas Brusamarello, Roberto da Silva, Ricardo A. L. Reis, Gilson I. Wirth |
Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Lucas Brusamarello, Roberto da Silva, Gilson I. Wirth, Ricardo A. L. Reis |
Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
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