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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6 occurrences of 6 keywords
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Results
Found 49 publication records. Showing 49 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Luis Entrena, Mario García-Valderas, Raúl Fernández Cardenal, Almudena Lindoso, Marta Portela-García, Celia López-Ongil |
Soft Error Sensitivity Evaluation of Microprocessors by Multilevel Emulation-Based Fault Injection.  |
IEEE Trans. Computers  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena |
Fault Injection in Modern Microprocessors Using On-Chip Debugging Infrastructures. |
IEEE Trans. Dependable Sec. Comput. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anna Vaskova, Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena |
Evaluation techniques for on-line testing of robust systems based on critical tasks distribution. |
IOLTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anna Vaskova, Celia López-Ongil, Enrique San Millán, Alejandro Jiménez-Horas, Luis Entrena |
Accelerating secure circuit design with hardware implementation of Diehard Battery of tests of randomness. |
IOLTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Honorio Martin, Enrique San Millán, Luis Entrena, Julio César Hernández Castro, Pedro Peris-Lopez |
AKARI-X: A pseudorandom number generator for secure lightweight systems. |
IOLTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Anna Vaskova, Celia López-Ongil, Alejandro Jiménez-Horas, Enrique San Millán, Luis Entrena |
Robust cryptographic ciphers with on-line statistical properties validation. |
IOLTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Michelangelo Grosso, Matteo Sonza Reorda, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena |
An on-line fault detection technique based on embedded debug features. |
IOLTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario García-Valderas, Luis Entrena, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García |
SET Emulation Under a Quantized Delay Model. |
J. Electronic Testing |
2009 |
DBLP DOI BibTeX RDF |
Fault emulation, Fault tolerance, Fault injection, Single event transients |
| 1 | Fabian Vargas, Claudia A. Rocha, Bernardo Pianta, Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena |
Briefing power/reliability optimization in embedded software design. |
IOLTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena |
In-depth analysis of digital circuits against soft errors for selective hardening. |
IOLTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Alejandro Jiménez-Horas, Enrique San Millán, Celia López-Ongil, Marta Portela-García, Mario García-Valderas, Luis Entrena |
Pseudo-random number generation applied to robust modern cryptography: A new technique for block ciphers. |
IOLTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Almudena Lindoso, Luis Entrena, Juan Izquierdo, Judith Liu-Jimenez |
Coarse-grain dynamically reconfigurable coprocessor for image processing in SOPC. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Enrique San Millán, Luis Entrena, José Alberto Espejo |
Logic Transformations by Multiple Wire Network Addition. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Celia López-Ongil, Alejandro Jiménez-Horas, Marta Portela-García, Mario García-Valderas, Enrique San Millán, Luis Entrena |
Smart Hardening for Round-based Encryption Algorithms: Application to Advanced Encryption Standard. |
IOLTS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Almudena Lindoso, Luis Entrena |
High performance FPGA-based image correlation. |
J. Real-Time Image Processing |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael G. Lorenz, Luis Mengibar, Enrique San Millán, Luis Entrena |
Low power data processing system with self-reconfigurable architecture. |
Journal of Systems Architecture |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez |
Wavelet-Based Fingerprint Region Selection. |
CAIP |
2007 |
DBLP DOI BibTeX RDF |
Biometrics, wavelet, Fingerprint |
| 1 | Almudena Lindoso, Luis Entrena, Judith Liu-Jimenez, Enrique San Millán |
Correlation-Based Fingerprint Matching with Orientation Field Alignment. |
ICB |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena |
SET Emulation Under a Quantized Delay Model. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Marta Portela-García, Celia López-Ongil, Mario García-Valderas, Luis Entrena |
A Rapid Fault Injection Approach for Measuring SEU Sensitivity in Complex Processors. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes |
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Matteo Sonza Reorda, Luca Sterpone, Massimo Violante, Marta Portela-García, Celia López-Ongil, Luis Entrena |
Fault Injection-based Reliability Evaluation of SoPCs. |
European Test Symposium |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena |
Emulation-based Fault Injection in Circuits with Embedded Memories. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario García-Valderas, Marta Portela-García, Celia López-Ongil, Luis Entrena-Arrontes |
An Extension of Transient Fault Emulation Techniques to Circuits with Embedded Memories. |
DDECS |
2006 |
DBLP BibTeX RDF |
|
| 1 | Almudena Lindoso, Luis Entrena, Celia López-Ongil, Judith Liu-Jimenez |
Correlation-Based Fingerprint Matching Using FPGAs. |
FPT |
2005 |
DBLP BibTeX RDF |
|
| 1 | Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes |
An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation. |
FPL |
2005 |
DBLP BibTeX RDF |
|
| 1 | Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes |
Techniques for Fast Transient Fault Grading Based on Autonomous Emulation. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Celia López-Ongil, Mario García-Valderas, Marta Portela-García, Luis Entrena-Arrontes |
Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael G. Lorenz, Luis Mengibar, Mario García-Valderas, Luis Entrena |
Power Consumption Reduction Through Dynamic Reconfiguration. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Celia López-Ongil, Raul Sánchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis Entrena |
FPGA Implementation of Biometric Authentication System Based on Hand Geometry. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Raul Sánchez-Reillo, Judith Liu-Jimenez, Luis Entrena |
Architectures for Biometric Match-on-Token Solutions. |
ECCV Workshop BioAW |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Mario García-Valderas, Celia López-Ongil, Marta Portela-García, Luis Entrena |
Transient Fault Emulation of Hardened Circuits in FPGA Platforms. |
IOLTS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López |
Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. |
Journal of Systems Architecture |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael G. Lorenz, Luis Mengibar, Luis Entrena, Raul Sánchez-Reillo |
Data Processing System With Self-reconfigurable Architecture, for Low Cost, Low Power Applications. |
FPL |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Mengibar, Luis Entrena, Michael G. Lorenz, Raul Sánchez-Reillo |
State Encoding for Low-Power FSMs in FPGA. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López |
An Industrial Environment for High-Level Fault-Tolerant Structures Insertion and Validation. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Berrojo, Isabel González, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Luis Entrena, Celia López |
New Techniques for Speeding-Up Fault-Injection Campaigns. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Berrojo, Isabel González, Luis Entrena, Celia López, Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero |
Analysis of the Equivalences and Dominances of Transient Faults at the RT Level. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Enrique San Millán, Luis Entrena, José Alberto Espejo |
On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. |
DSD |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías |
Functional extension of structural logic optimization techniques. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías |
Generalized reasoning scheme for redundancy addition and removal logic optimization. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo |
Logic Optimization of Unidirectional Circuits with Structural Methods. |
IOLTW |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Entrena, Celia López, Emilio Olías |
Automatic Insertion of Fault-Tolerant Structures at the RT Level. |
IOLTW |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Enrique San Millán, Luis Entrena, José Alberto Espejo |
On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. |
ICCAD |
2001 |
DBLP BibTeX RDF |
|
| 1 | Enrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno |
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías |
Logic Restructuring for MUX-Based FPGAs. |
EUROMICRO |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Serafín Olcoz, Luis Entrena, Luis Berrojo |
An effective system development environment based on VHDL prototyping. |
EURO-DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Entrena-Arrontes, Kwang-Ting Cheng |
Combinational and sequential logic optimization by redundancy addition and removal. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Luis Entrena, Kwang-Ting Cheng |
Sequential logic optimization by redundancy addition and removal. |
ICCAD |
1993 |
DBLP DOI BibTeX RDF |
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