Search results for "M. B. Srinivas"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A Prefix Based Reconfigurable Adder.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A Unified Architecture for BCD and Binary Adder/Subtractor.	DSD	2011	DBLP DOI BibTeX RDF
1	Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, M. B. Srinivas	An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Mahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A Novel, Variable Resolution Flash ADC with Sub Flash Architecture.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	P. Jamwal, M. B. Srinivas, G. V. K. Sarma, M. M. Krishna	A new approach to minimize leakage power in nano-scale VLSI adder.	ICWET	2010	DBLP DOI BibTeX RDF
1	Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A low power, variable resolution two-step flash ADC.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	two-step flash ADC, variable resolution, low power
1	Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas	An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.	VLSI Design	2010	DBLP DOI BibTeX RDF	delay reduction, Schmitt Trigger, Buffer Insertion, Power reduction
1	Vasanth Iyer, S. Sitharama Iyengar, Garimella Rama Murthy, Nandan Parameswaran, Dhananjay Singh, Mandalika B. Srinivas	Effects of channel SNR in mobile cognitive radios and coexisting deployment of cognitive wireless sensor networks.	IPCCC	2010	DBLP DOI BibTeX RDF
1	Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas	A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas	Efficient Reversible Logic Design of BCD Subtractors.	Transactions on Computational Science	2009	DBLP DOI BibTeX RDF	BCD subtractors, BCD adders, Reversible logic
1	Vasanth Iyer, S. Sitharama Iyengar, Garimella Rama Murthy, Bertrand Hochet, Vir V. Phoha, M. B. Srinivas	Multi-hop scheduling and local data link aggregation dependant Qos in modeling and simulation of power-aware wireless sensor networks.	IWCMC	2009	DBLP DOI BibTeX RDF	MAC layer duty-cycling, QoS for link quality, renewable energy resources, wireless sensor network, distributed algorithms, algorithm complexity, power aware routing
1	Swathi Ramasahayam, M. B. Srinivas	All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas	A High Performance Unified BCD and Binary Adder/Subtractor.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas	Design of a Low Power, Variable-Resolution Flash ADC.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas	A novel low power, variable resolution pipelined ADC.	SoCC	2009	DBLP DOI BibTeX RDF
1	Abinesh Ramachandran, Bharghava Rajaram, Mandalika B. Srinivas	Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	bus coding, delay, process variation
1	Lingamneni Avinash, Kirthi Krishna Muntimadugu, M. B. Srinivas	A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	J. V. R. Ravindra, M. B. Srinivas	Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	krylov subspace techniques, monte-carlo simulation, model order reduction, rlc
1	Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas	A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Vasanth Iyer, Rammurthy Garimella, M. B. Srinivas	Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks.	SUTC	2008	DBLP DOI BibTeX RDF	Sensor Networks, Reliability, Compression, Fault-tolerant algorithms
1	M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas	New and Improved Architectures for Montgomery Modular Multiplication.	MONET	2007	DBLP DOI BibTeX RDF	reconfigurable multiplier, scalable multiplier, RSA, ECC, carry save adders, Montgomery modular multiplication
1	J. V. R. Ravindra, M. B. Srinivas	Delay and Energy Efficient Coding Techniques for Capacitive Interconnects.	Journal of Circuits, Systems, and Computers	2007	DBLP DOI BibTeX RDF
1	Keerthi Laal Kala, M. B. Srinivas	Rule Selection in Fuzzy Systems using Heuristics and Branch Prediction.	FOCI	2007	DBLP DOI BibTeX RDF
1	Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas	A Comparative Study of Different FFT Architectures for Software Defined Radio.	SAMOS	2007	DBLP DOI BibTeX RDF
1	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas	Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Sudhakar Maddi, M. B. Srinivas	A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA.	SBCCI	2007	DBLP DOI BibTeX RDF	sum-carry logic, RSA, ECC, reconfigurable architectures, montgomery multiplication, unified architectures
1	K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas	Bus encoding schemes for minimizing delay in VLSI interconnects.	SBCCI	2007	DBLP DOI BibTeX RDF	bus encoding technique, crosstalk class, delay, encoder, decoder, VLSI interconnects
1	J. V. R. Ravindra, M. B. Srinivas	A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects.	DSD	2007	DBLP DOI BibTeX RDF
1	M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas	A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	bit transitions, bus-encoding scheme, high impedance state, simultaneous switching noise (SSN), spatial and temporal redundancy, low power, delay, encoder, decoder, crosstalk noise, inductive coupling
1	Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas	Novel architectures for efficient (m, n) parallel counters.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	low power, multiplexer, high speed, parallel counters
1	Shashank Mittal, Md. Zafar Ali Khan, M. B. Srinivas	Area Efficient High Speed Architecture of Bruun's FFT for Software Defined Radio.	GLOBECOM	2007	DBLP DOI BibTeX RDF
1	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	M. Sudhakar, Ramachandruni Venkata Kamala, M. B. Srinivas	A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n).	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN).	ISCAS	2007	DBLP DOI BibTeX RDF
1	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel High-Speed Redundant Binary to Binary converter using Prefix Networks.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Himanshu Thapliyal, Hamid R. Arabnia, M. B. Srinivas	Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format	CoRR	2006	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas	VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics	CoRR	2006	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas	Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU	CoRR	2006	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas	An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates	CoRR	2006	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas	Novel Reversible Multiplier Architecture Using Reversible TSG Gate	CoRR	2006	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas	A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits	CoRR	2006	DBLP BibTeX RDF
1	Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas	Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format	CoRR	2006	DBLP BibTeX RDF
1	K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas	Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method.	DELTA	2006	DBLP DOI BibTeX RDF	Simultaneous Switching Noise (SSN), Odd Simultaneous Transitions (OST), Even Simultaneous Transitions (EST), VLSI, Low power, Coding
1	Himanshu Thapliyal, Anvesh Ramasahayam, Vivek Reddy Kotha, Kunul Gottimukkula, M. B. Srinivas	Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder.	DELTA	2006	DBLP DOI BibTeX RDF
1	Ramachandruni Venkata Kamala, M. Sudhakar, M. B. Srinivas	An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n).	DSD	2006	DBLP DOI BibTeX RDF
1	Ramachandruni Venkata Kamala, M. B. Srinivas	High-Throughput Montgomery Modular Multiplication.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas	The New BCD Subtractor and Its Reversible Logic Implementation.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
1	Pallavi Devi Gopineedi, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia	Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations.	ESA	2006	DBLP BibTeX RDF
1	Keerthi Laal Kala, M. B. Srinivas	A Generic Architecture for Intelligent System Hardware.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Himanshu Thapliyal, Saurabh Kotiyal, M. B. Srinivas	Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas	A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas	Novel Reversible Multiplier Architecture Using Reversible TSG Gate.	AICCSA	2006	DBLP DOI BibTeX RDF
1	Himanshu Thapliyal, Neela Gopi, K. K. Pavan Kumar, M. B. Srinivas	Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture.	AICCSA	2006	DBLP DOI BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia	Design for A Fast And Low Power 2's Complement Multiplier.	CDES	2005	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia	Verilog Coding Style for Efficient Synthesis In FPGA.	CDES	2005	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia	Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture.	AMCS	2005	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas	A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
1	Saurabh Kotiyal, Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia	VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison.	CSC	2005	DBLP BibTeX RDF
1	Keerthi Laal Kala, M. B. Srinivas	A 32-Bit Binary Floating Point Neuro-Chip.	ICNC	2005	DBLP DOI BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia	Implementation of A Fast Square In RSA Encryption/Decryption Architecture.	Security and Management	2005	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia	Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier.	Security and Management	2005	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia	Reversible Logic Synthesis of Half, Full and Parallel Subtractors.	ESA	2005	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia	A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs.	ESA	2005	DBLP BibTeX RDF
1	Himanshu Thapliyal, M. B. Srinivas, Hamid R. Arabnia	A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor.	ESA	2005	DBLP BibTeX RDF
1	K. S. Sainarayanan, J. V. R. Ravindra, M. B. Srinivas	A novel deep submicron low power bus coding technique.	Circuits, Signals, and Systems	2005	DBLP BibTeX RDF
1	Yaswanth Narvaneni, M. B. Srinivas	Local Language Support for Handheld Devices.	ITCC	2005	DBLP DOI BibTeX RDF

Publications of M. B. Srinivas Mandalika B. Srinivas ( http://dblp.L3S.de/Authors/M._B._Srinivas )