Search results for "M. Balakrishnan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Sonali Chouhan, M. Balakrishnan, Ranjan Bose	System-Level Design Space Exploration Methodology for Energy-Efficient Sensor Node Configurations: An Experimental Validation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Preeti Ranjan Panda, M. Balakrishnan, Anant Vishnoi	Compressing Cache State for Postsilicon Processor Debug.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Rajeswari Devadoss, Kolin Paul, M. Balakrishnan	p-QCA: A Tiled Programmable Fabric Architecture Using Molecular Quantum-Dot Cellular Automata.	JETC	2011	DBLP DOI BibTeX RDF
1	Rajeswari Devadoss, Kolin Paul, M. Balakrishnan	Architecture and tools for programmable QCA.	FPT	2011	DBLP DOI BibTeX RDF
1	Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan	Enhancing post-silicon processor debug with Incremental Cache state Dumping.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Rajeswari Devadoss, Kolin Paul, M. Balakrishnan	A tiled programmable fabric using QCA.	FPT	2010	DBLP DOI BibTeX RDF
1	Rajeswari Devadoss, Kolin Paul, M. Balakrishnan	Clocking-Based Coplanar Wire Crossing Scheme for QCA.	VLSI Design	2010	DBLP DOI BibTeX RDF	Quantum Cellular Automata, Wire Crossing, Coplanar, Low Power, Clocking, Crossover, QCA, Quantum-dot Cellular Automata
1	Sonali Chouhan, Ranjan Bose, M. Balakrishnan	Integrated energy analysis of error correcting codes and modulation for energy efficient wireless sensor nodes.	IEEE Transactions on Wireless Communications	2009	DBLP DOI BibTeX RDF
1	Sonali Chouhan, Ranjan Bose, M. Balakrishnan	A Framework for Energy-Consumption-Based Design Space Exploration for Wireless Sensor Nodes.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Sonali Chouhan, M. Balakrishnan, Ranjan Bose	An experimental validation of system level design space exploration methodology for energy efficient sensor nodes.	ISLPED	2009	DBLP DOI BibTeX RDF	computation-radio energy trade-off, wireless sensor networks, error correcting codes, low energy, energy measurement
1	Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan	Online cache state dumping for processor debug.	DAC	2009	DBLP DOI BibTeX RDF	cache compression, processor debug, silicon debug, design for debug, post-silicon validation
1	Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan	Cache aware compression for processor debug support.	DATE	2009	DBLP BibTeX RDF
1	Aryabartta Sahu, M. Balakrishnan, Preeti Ranjan Panda	A generic platform for estimation of multi-threaded program performance on heterogeneous multiprocessors.	DATE	2009	DBLP BibTeX RDF
1	Sonali Chouhan, M. Balakrishnan, Ranjan Bose	A framework for energy consumption based design space exploration for wireless sensor nodes.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar	Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.	International Journal of Parallel Programming	2007	DBLP DOI BibTeX RDF	Performance evaluation, VLIW, ASIP, Clustered VLIW processors
1	Anup Gangwar, M. Balakrishnan, Anshul Kumar	Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	performance evaluation, VLIW, ASIP, clustered VLIW processors
1	Ashutosh Pal, M. Balakrishnan	A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures.	FPL	2007	DBLP DOI BibTeX RDF
1	M. Balakrishnan, N. Ravisankar, K. Meena, R. Elanchezhian, S. K. Zamir Ahmed	Yield Prediction Through Feed Forward Neural Network Approach for Direct Seeded Rice (Oryza sativa) in Bay Islands.	IICAI	2007	DBLP BibTeX RDF
1	Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar	Rapid Resource-Constrained Hardware Performance Estimation.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
1	Harsh Dhand, Basant Kumar Dwivedi, M. Balakrishnan	New approach to architectural synthesis: incorporating QoS constraint.	EMSOFT	2006	DBLP DOI BibTeX RDF	soft real time constraints, quality of service, partitioning, mapping, process network
1	Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra	Sequential Equivalence Checking.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	M. Balakrishnan, B. S. Panwar	A Specialized Graduate Program in VLSI Design Tools and Technology.	MSE	2005	DBLP DOI BibTeX RDF
1	Ankit Mathur, Mayank Agarwal, Soumyadeb Mitra, Anup Gangwar, M. Balakrishnan, Subhashis Banerjee	SMPS: an FPGA-based prototyping environment for multiprocessor embedded systems (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
1	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	Integrated On-Chip Storage Evaluation in ASIP Synthesis.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M. Balakrishnan	ADOPT: An Approach to Activity Based Delay Optimization.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar	Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.	DATE	2005	DBLP DOI BibTeX RDF
1	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP design.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan	Synthesis of Application Specific Multiprocessor Architectures for Process Networks.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan	Automatic synthesis of system on chip multiprocessor architectures for process networks.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	application specific multiprocessors, partitioning, Kahn process networks
1	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	Exploring Storage Organization in ASIP Synthesis.	DSD	2003	DBLP DOI BibTeX RDF
1	Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar	SoC Synthesis with Automatic Hardware Software Interface Generation.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP synthesis.	CASES	2002	DBLP DOI BibTeX RDF	ASIP Synthesis, retargetable estimation, storage exploration, design space exploration, instruction scheduling, register file, global analysis, register spill, liveness analysis
1	M. Balakrishnan, Peter Marwedel, Lars Wehmeyer, Nils Grunwald, Rajeshwari Banakar, Stefan Steinke	Reducing Energy Consumption by Dynamic Copying of Instructions onto Onchip Memory.	ISSS	2002	DBLP DOI BibTeX RDF	onchip memory, energy optimization
1	M. Balakrishnan, Anshul Kumar, C. P. Joshi	A New Performance Evaluation Approach for System Level Design Space Exploration.	ISSS	2002	DBLP DOI BibTeX RDF	design space exploration, system level design, statistical simulation
1	M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha	A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.	ISSS	2002	DBLP DOI BibTeX RDF	Trimaran, performance, design space exploration, VLIW, ASIP
1	Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar	Exploring the Number of Register Windows in ASIP Synthesis.	VLSI Design	2002	DBLP DOI BibTeX RDF	Regular language recognition, Processor and memory configuration, ASIP Synthesis, Context switch, Register windows
1	Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan	A New Divide and Conquer Method for Achieving High Speed Division in Hardware.	VLSI Design	2002	DBLP DOI BibTeX RDF	Carry Propagate Adders, Pipelineability, Throughput, Latency, Rounding, Carry Save Adders, Radix, SRT
1	Rajeshwari Banakar, Stefan Steinke, Bo-Sik Lee, M. Balakrishnan, Peter Marwedel	Scratchpad memory: design alternative for cache on-chip memory in embedded systems.	CODES	2002	DBLP DOI BibTeX RDF	Cactis, SCRATCHPAD
1	Lars Wehmeyer, Manoj Kumar Jain, Stefan Steinke, Peter Marwedel, M. Balakrishnan	Analysis of the influence of register file size on energyconsumption, code size, and execution time.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	M. Balakrishnan	A Specialized Graduate Program in VLSI Design: A Success Story. (PDF / PS)	MSE	2001	DBLP DOI BibTeX RDF
1	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	ASIP Design Methodologies : Survey and Issues.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Anupam Rastogi, M. Balakrishnan, Anshul Kumar	Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Basant Kumar Dwivedi, Jan Hoogerbrugge, Paul Stravers, M. Balakrishnan	Exploring design space of parallel realizations: MPEG-2 decoder case study.	CODES	2001	DBLP DOI BibTeX RDF	MPEG-2 decoder, YAPI, parallel realization, process, thread, FIFO
1	Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, Peter Marwedel, M. Balakrishnan	Evaluating register file size in ASIP design.	CODES	2001	DBLP DOI BibTeX RDF	instruction power model, synthesis, application specific instruction set processor, instruction set, register file, register spill
1	M. Balakrishnan, Heman Khanna	Allocation of FIFO structures in RTL data paths.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	synthesis, RTL, ILP, FIFO, data path
1	Akshaye Sama, J. F. M. Theeuwen, M. Balakrishnan	Speeding up power estimation of embedded software.	ISLPED	2000	DBLP DOI BibTeX RDF
1	Arvind Rajawat, M. Balakrishnan, Anshul Kumar	nterface Synthesis: Issues and Approaches.	VLSI Design	2000	DBLP DOI BibTeX RDF	Codesign methodology, Interface optimization, Communication protocols, Interface synthesis
1	Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Shashi Kumar, M. Balakrishnan	Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming.	VLSI Design	2000	DBLP DOI BibTeX RDF
1	T. Vinod Kumar Gupta, Purvesh Sharma, M. Balakrishnan, Sharad Malik	Processor Evaluation in an Embedded Systems Design Environment.	VLSI Design	2000	DBLP DOI BibTeX RDF	ASAP scheduler, Architecture constrained scheduler, ASIP, Processor architecture, Real-time constraints, Application profiling
1	M. Anand, Sanjiv Kapoor, M. Balakrishnan	Hardware/Software Partitioning Between Microprocessor and Reconfigurable Hardware.	FPGA	1999	DBLP DOI BibTeX RDF
1	Ajoy C. Siddabathuni, M. Balakrishnan	Simulation and Modeling of a Multicast ATM Switch.	VLSI Design	1999	DBLP BibTeX RDF
1	Rashmi Goswami, V. Srinivasan, M. Balakrishnan	MPEG-2 Video Data Simulator: A Case Study in Constrained HW-SW Codesign.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	A. R. Naseer, M. Balakrishnan, Anshul Kumar	Direct mapping of RTL structures onto LUT-based FPGA's.	IEEE Trans. on CAD of Integrated Circuits and Systems	1998	DBLP DOI BibTeX RDF
1	Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar	Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library.	VLSI Design	1998	DBLP BibTeX RDF
1	Sandeep K. Lodha, Shashank Gupta, M. Balakrishnan, Subhashis Banerjee	Real Time Collision Detection and Avoidance: A Case Study for Design Space Exploration in HW-SW Codesign.	VLSI Design	1998	DBLP BibTeX RDF
1	M. Balakrishnan, R. Cohen	Global Optimization of Multiplexed Video Encoders. (PDF / PS)	ICIP	1997	DBLP DOI BibTeX RDF	multiplexed video encoders, multiple variable rate video encoders, constant bit-rate channel, complex video processing, channel rate, target rate, VBR coding, global optimization, video coding, rate controller, video quality, buffer constraints
1	Heman Khanna, M. Balakrishnan	Allocation of FIFO Structures in RTL Data Paths.	VLSI Design	1997	DBLP DOI BibTeX RDF
1	Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar	A Novel Reconfigurable Co-Processor Architecture.	VLSI Design	1997	DBLP DOI BibTeX RDF
1	A. R. Naseer, M. Balakrishnan, Anshul Kumar	Optimal Clock Period for Synthesized Data Paths.	VLSI Design	1997	DBLP DOI BibTeX RDF
1	A. R. Naseer, M. Balakrishnan, Anshul Kumar	Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs.	FPL	1995	DBLP DOI BibTeX RDF
1	M. Balakrishnan	Buffer constraints in a variable-rate packetized video system. (PDF / PS)	ICIP	1995	DBLP DOI BibTeX RDF	variable rate codes, variable rate packetized video system, variable rate video encoding system, encoder buffer control mechanism, decoder buffers, logical buffer sizes, channel rate, algorithm, video coding, packet switching, decoding, buffer storage, telecommunication control, necessary conditions, buffer constraints
1	Alok Kumar, Anshul Kumar, M. Balakrishnan	Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis.	VLSI Design	1995	DBLP DOI BibTeX RDF	heuristic search based approach, VITAL, partial binding sub-tasks, design styles, component types, scheduling, scheduling, computational complexity, VLSI, high level synthesis, search problems, cost estimates, allocation, computation time, binding, design constraints, solution quality, data path synthesis, benchmark designs
1	A. R. Naseer, M. Balakrishnan, Anshul Kumar	An Efficient Technique for Mapping RTL Structures onto FPGAs.	FPL	1994	DBLP DOI BibTeX RDF
1	Atul Varshneya, B. B. Madan, M. Balakrishnan	Concurrent Search and Insertion in K-Dimensional Height Balanced Trees.	IPPS	1994	DBLP BibTeX RDF
1	A. R. Naseer, M. Balakrishnan, Anshul Kumar	FAST: FPGA Targeted RTL Structure Synthesis Technique.	VLSI Design	1994	DBLP BibTeX RDF
1	M. V. Rao, M. Balakrishnan, Anshul Kumar	DESSERT: Design Space Exploration of RT Level Components.	VLSI Design	1993	DBLP BibTeX RDF
1	C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer	High Level Design Experiences with IDEAS.	VLSI Design	1993	DBLP BibTeX RDF
1	M. Balakrishnan, Peter Marwedel	Integrated Scheduling and Binding: A Synthesis Approach for Design Space Exploration.	DAC	1989	DBLP DOI BibTeX RDF
1	M. Balakrishnan, S. Sutarwala, Arun K. Majumdar, Dilip K. Banerji, James G. Linders	A Semantic Approach for Modular Synthesis of VLSI Systems.	Inf. Process. Lett.	1988	DBLP DOI BibTeX RDF
1	M. Balakrishnan, Arun K. Majumdar, Dilip K. Banerji, James G. Linders, Jayanti C. Majithia	Allocation of multiport memories in data path synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	1988	DBLP DOI BibTeX RDF

Publications of "M. Balakrishnan" ( http://dblp.L3S.de/Authors/M._Balakrishnan )