Search results for "MICRO"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Nikolas Ioannou, Marcelo Cintra	Complementing user-level coarse-grain parallelism with implicit speculative parallelism.	MICRO	2011	DBLP DOI BibTeX RDF
1	Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter	Active management of timing guardband to save energy in POWER7.	MICRO	2011	DBLP DOI BibTeX RDF
1	Konstantinos Aisopos, Li-Shiuan Peh	A systematic methodology to develop resilient cache coherence protocols.	MICRO	2011	DBLP DOI BibTeX RDF
1	Mitchell Hayenga, Mikko H. Lipasti	The NoX router.	MICRO	2011	DBLP DOI BibTeX RDF
1	Jason Mars, Lingjia Tang, Robert Hundt, Kevin Skadron, Mary Lou Soffa	Bubble-Up: increasing utilization in modern warehouse scale computers via sensible co-locations.	MICRO	2011	DBLP DOI BibTeX RDF
1	Ganesh Venkatesh, Jack Sampson, Nathan Goulding-Hotta, Sravanthi Kota Venkata, Michael Bedford Taylor, Steven Swanson	QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores.	MICRO	2011	DBLP DOI BibTeX RDF
1	Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer	PACMan: prefetch-aware cache management for high performance caching.	MICRO	2011	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi	Pay-As-You-Go: low-overhead hard-error correction for phase change memories.	MICRO	2011	DBLP DOI BibTeX RDF
1	Yuanrui Zhang, Wei Ding, Mahmut T. Kandemir, Jun Liu, Ohyoung Jang	A data layout optimization framework for NUCA-based multicores.	MICRO	2011	DBLP DOI BibTeX RDF
1	Yan Pan, John Kim, Gokhan Memik	FeatherWeight: low-cost optical arbitration with QoS support.	MICRO	2011	DBLP DOI BibTeX RDF
1	Mark Gebhart, Stephen W. Keckler, William J. Dally	A compile-time managed multi-level register file hierarchy.	MICRO	2011	DBLP DOI BibTeX RDF
1	Sheng Li, Kevin T. Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi	System-level integrated server architectures for scale-out datacenters.	MICRO	2011	DBLP DOI BibTeX RDF
1	Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott A. Mahlke, David I. August	Encore: low-cost, fine-grained transient fault recovery.	MICRO	2011	DBLP DOI BibTeX RDF
1	Qing Guo, Xiaochen Guo, Yuxin Bai, Engin Ipek	A resistive TCAM accelerator for data-intensive computing.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gregory Frederick Diamos, Benjamin Ashbaugh, Subramaniam Maiyuran, Andrew Kerr, Haicheng Wu, Sudhakar Yalamanchili	SIMD re-convergence at thread frontiers.	MICRO	2011	DBLP DOI BibTeX RDF
1	Jing Xin, Russ Joseph	Identifying and predicting timing-critical instructions to boost timing speculation.	MICRO	2011	DBLP DOI BibTeX RDF
1	Carlo Galuzzi, Luigi Carro, Andreas Moshovos, Milos Prvulovic (eds.)	44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, 3-7 December 2011, Porto Alegre, Brazil	MICRO	2011	DBLP BibTeX RDF
1	André Seznec	A new case for the TAGE branch predictor.	MICRO	2011	DBLP DOI BibTeX RDF
1	George Michelogiannakis, Nan Jiang, Daniel U. Becker, William J. Dally	Packet chaining: efficient single-cycle allocation for on-chip networks.	MICRO	2011	DBLP DOI BibTeX RDF
1	Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt	Improving GPU performance via large warps and two-level warp scheduling.	MICRO	2011	DBLP DOI BibTeX RDF
1	Marc de Kruijf, Karthikeyan Sankaralingam	Idempotent processor architecture.	MICRO	2011	DBLP DOI BibTeX RDF
1	Seongwook Jin, Jeongseob Ahn, Sanghoon Cha, Jaehyuk Huh	Architectural support for secure virtualization under a vulnerable hypervisor.	MICRO	2011	DBLP DOI BibTeX RDF
1	Andrew Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger	Preventing PCM banks from seizing too much power.	MICRO	2011	DBLP DOI BibTeX RDF
1	Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke, David I. August	Bundled execution of recurring traces for energy-efficient general purpose processing.	MICRO	2011	DBLP DOI BibTeX RDF
1	Michael Ferdman, Cansu Kaynak, Babak Falsafi	Proactive instruction fetch.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	A register-file approach for row buffer caches in die-stacked DRAMs.	MICRO	2011	DBLP DOI BibTeX RDF
1	Christopher Nitta, Matthew K. Farrens, Venkatesh Akella	Resilient microring resonator based photonic networks.	MICRO	2011	DBLP DOI BibTeX RDF
1	Jesse G. Beu, Michel C. Rosier, Thomas M. Conte	Manager-client pairing: a framework for implementing coherence hierarchies.	MICRO	2011	DBLP DOI BibTeX RDF
1	Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González	Accelerating microprocessor silicon validation by exposing ISA diversity.	MICRO	2011	DBLP DOI BibTeX RDF
1	Soontae Kim, Jongmin Lee 0002, Jesung Kim, Seokin Hong	Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gilles Pokam, Cristiano Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin Emile Gottschlich, Jungwoo Ha, Youfeng Wu	CoreRacer: a practical memory race recorder for multicore x86 TSO processors.	MICRO	2011	DBLP DOI BibTeX RDF
1	Tushar Krishna, Li-Shiuan Peh, Bradford M. Beckmann, Steven K. Reinhardt	Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication.	MICRO	2011	DBLP DOI BibTeX RDF
1	Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John	Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era.	MICRO	2011	DBLP DOI BibTeX RDF
1	Vignyan Reddy Kothinti Naresh, David J. Palframan, Mikko H. Lipasti	CRAM: coded registers for amplified multiporting.	MICRO	2011	DBLP DOI BibTeX RDF
1	Ritesh Parikh, Valeria Bertacco	Formally enhanced runtime verification to ensure NoC functional correctness.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gabriel H. Loh, Mark D. Hill	Efficiently enabling conventional block sizes for very large die-stacked DRAM caches.	MICRO	2011	DBLP DOI BibTeX RDF
1	Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer	SHiP: signature-based hit predictor for high performance caching.	MICRO	2011	DBLP DOI BibTeX RDF
1	Wilson W. L. Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt	Hardware transactional memory for GPU architectures.	MICRO	2011	DBLP DOI BibTeX RDF
1	Ahmed H. Abdel-Gawad, Mithuna Thottethodi	TransCom: transforming stream communication for load balance and efficiency in networks-on-chip.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gagan Gupta, Gurindar S. Sohi	Dataflow execution of sequential imperative programs on multicore architectures.	MICRO	2011	DBLP DOI BibTeX RDF
1	Zhenyu Sun, Xiuyuan Bi, Hai Helen Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu	Multi retention level STT-RAM cache designs with a dynamic refresh scheme.	MICRO	2011	DBLP DOI BibTeX RDF
1	Jiaqi Zhang, Weiwei Xiong, Yang Liu, Soyeon Park, Yuanyuan Zhou, Zhiqiang Ma	ATDetector: improving the accuracy of a commercial data race detector by identifying address transfer.	MICRO	2011	DBLP DOI BibTeX RDF
1	Ryan Cochran, Can Hankendi, Ayse Kivilcim Coskun, Sherief Reda	Pack & Cap: adaptive DVFS and thread packing under power caps.	MICRO	2011	DBLP DOI BibTeX RDF
1	Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut T. Kandemir, Thomas Moscibroda	Reducing memory interference in multicore systems via application-aware memory channel partitioning.	MICRO	2011	DBLP DOI BibTeX RDF
1	Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt	Parallel application memory scheduling.	MICRO	2011	DBLP DOI BibTeX RDF
1	Adrian Nistor, Darko Marinov, Josep Torrellas	InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, Richard W. Vuduc	Many-Thread Aware Prefetching Mechanisms for GPGPU Applications.	MICRO	2010	DBLP DOI BibTeX RDF
1	Abdullah Muzahid, Norimasa Otsuki, Josep Torrellas	AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection.	MICRO	2010	DBLP DOI BibTeX RDF
1	Hanjun Kim, Arun Raman, Feng Liu, Jae W. Lee, David I. August	Scalable Speculative Parallelization on Commodity Clusters.	MICRO	2010	DBLP DOI BibTeX RDF
1	Utku Aydonat, Tarek S. Abdelrahman	Hardware Support for Relaxed Concurrency Control in Transactional Memory.	MICRO	2010	DBLP DOI BibTeX RDF
1	Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero	Task Superscalar: An Out-of-Order Task Pipeline.	MICRO	2010	DBLP DOI BibTeX RDF
1	Timothy N. Miller, Renji Thomas, James Dinan, Bruce M. Adcock, Radu Teodorescu	Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches.	MICRO	2010	DBLP DOI BibTeX RDF
1	Rajkishore Barik, Jisheng Zhao, Vivek Sarkar	Efficient Selection of Vector Instructions Using Dynamic Programming.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong, Murali Annavaram, Michel Dubois	Adaptive and Speculative Slack Simulations of CMPs on CMPs.	MICRO	2010	DBLP DOI BibTeX RDF
1	Adrian M. Caulfield, Arup De, Joel Coburn, Todor I. Mollow, Rajesh K. Gupta, Steven Swanson	Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories.	MICRO	2010	DBLP DOI BibTeX RDF
1		43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA	MICRO	2010	DBLP BibTeX RDF
1	Minseon Ahn, Eun Jung Kim	Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jae-Woong Chung, Luke Yen, Stephan Diestelhorst, Martin Pohlack, Michael Hohmuth, David Christie, Dan Grossman	ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory.	MICRO	2010	DBLP DOI BibTeX RDF
1	Samira Manabi Khan, Yingying Tian, Daniel A. Jiménez	Sampling Dead Block Prediction for Last-Level Caches.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jie Yu, Satish Narayanasamy	Tolerating Concurrency Bugs Using Transactions as Lifeguards.	MICRO	2010	DBLP DOI BibTeX RDF
1	Arun A. Nair, Lizy Kurian John, Lieven Eeckhout	AVF Stressmark: Towards an Automated Methodology for Bounding the Worst-Case Vulnerability to Soft Errors.	MICRO	2010	DBLP DOI BibTeX RDF
1	Minjang Kim, Hyesoon Kim, Chi-Keung Luk	SD3: A Scalable Approach to Dynamic Data-Dependence Profiling.	MICRO	2010	DBLP DOI BibTeX RDF
1	Thomas Vogelsang	Understanding the Energy Consumption of Dynamic Random Access Memories.	MICRO	2010	DBLP DOI BibTeX RDF
1	Shekhar Srikantaiah, Mahmut T. Kandemir	Synergistic TLBs for High Performance Address Translation in Chip Multiprocessors.	MICRO	2010	DBLP DOI BibTeX RDF
1	Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang	Memory Latency Reduction via Thread Throttling.	MICRO	2010	DBLP DOI BibTeX RDF
1	Xuehai Qian, Wonsun Ahn, Josep Torrellas	ScalableBulk: Scalable Cache Coherence for Atomic Blocks in a Lazy Environment.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jin Ouyang, Yuan Xie	LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support.	MICRO	2010	DBLP DOI BibTeX RDF
1	Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer	Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies.	MICRO	2010	DBLP DOI BibTeX RDF
1	Daniel Sanchez, Christos Kozyrakis	The ZCache: Decoupling Ways and Associativity.	MICRO	2010	DBLP DOI BibTeX RDF
1	Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh	Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric.	MICRO	2010	DBLP DOI BibTeX RDF
1	Michael M. Lee, John Kim, Dennis Abts, Michael R. Marty, Jae W. Lee	Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs.	MICRO	2010	DBLP DOI BibTeX RDF
1	Daehoon Kim, Hwanju Kim, Jaehyuk Huh	Virtual Snooping: Filtering Snoops in Virtualized Multi-cores.	MICRO	2010	DBLP DOI BibTeX RDF
1	Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke	Erasing Core Boundaries for Robust and Configurable Performance.	MICRO	2010	DBLP DOI BibTeX RDF
1	Ali Bakhoda, John Kim, Tor M. Aamodt	Throughput-Effective On-Chip Networks for Manycore Accelerators.	MICRO	2010	DBLP DOI BibTeX RDF
1	Dongyuan Zhan, Hong Jiang, Sharad C. Seth	STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches.	MICRO	2010	DBLP DOI BibTeX RDF
1	Enrique Vallejo, Ramón Beivide, Adrián Cristal, Tim Harris, Fernando Vallejo, Osman S. Unsal, Mateo Valero	Architectural Support for Fair Reader-Writer Locking.	MICRO	2010	DBLP DOI BibTeX RDF
1	Marc Lupon, Grigorios Magklis, Antonio González	A Dynamically Adaptable Hardware Transactional Memory.	MICRO	2010	DBLP DOI BibTeX RDF
1	Guoping Long, Diana Franklin, Susmit Biswas, Pablo J. Ortiz, Jason Oberg, Dongrui Fan, Frederic T. Chong	Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors.	MICRO	2010	DBLP DOI BibTeX RDF
1	Meng Zhang, Alvin R. Lebeck, Daniel J. Sorin	Fractal Coherence: Scalably Verifiable Cache Coherence.	MICRO	2010	DBLP DOI BibTeX RDF
1	Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith, Gu-Yeon Wei, David Brooks	Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling.	MICRO	2010	DBLP DOI BibTeX RDF
1	Syed Ali Raza Jafri, Yu-Ju Hong, Mithuna Thottethodi, T. N. Vijaykumar	Adaptive Flow Control for Robust Performance and Energy.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jeffrey Stuecheli, Dimitris Kaseridis, Hillery C. Hunter, Lizy K. John	Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory.	MICRO	2010	DBLP DOI BibTeX RDF
1	Aparna Kotha, Kapil Anand, Matthew Smithson, Greeshma Yellareddy, Rajeev Barua	Automatic Parallelization in a Binary Rewriter.	MICRO	2010	DBLP DOI BibTeX RDF
1	Michael Steffen, Joseph Zambreno	Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels.	MICRO	2010	DBLP DOI BibTeX RDF
1	Matthew A. Watkins, David H. Albonesi	ReMAP: A Reconfigurable Heterogeneous Multicore Architecture.	MICRO	2010	DBLP DOI BibTeX RDF
1	Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, Hsien-Hsin S. Lee	SAFER: Stuck-At-Fault Error Recovery for Memories.	MICRO	2010	DBLP DOI BibTeX RDF
1	Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla, Michael F. P. O'Boyle	A Predictive Model for Dynamic Microarchitectural Adaptivity Control.	MICRO	2010	DBLP DOI BibTeX RDF
1	Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai	Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?	MICRO	2010	DBLP DOI BibTeX RDF
1	Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mikko H. Lipasti	Combating Aging with the Colt Duty Cycle Equalizer.	MICRO	2010	DBLP DOI BibTeX RDF
1	Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai	Register Cache System Not for Latency Reduction Purpose.	MICRO	2010	DBLP DOI BibTeX RDF
1	Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter	Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior.	MICRO	2010	DBLP DOI BibTeX RDF
1	Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, J.-W. Lee, Xing Fang, Samuel P. Midkiff, David Wong	BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support.	MICRO	2009	DBLP DOI BibTeX RDF	atomic region, chunk-based architecture, compiler optimization, sequential consistency
1	Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt	Coordinated control of multiple prefetchers in multi-core systems.	MICRO	2009	DBLP DOI BibTeX RDF	prefetching, multi-core, feedback control, memory systems
1	Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang, Cristiano Pereira	Offline symbolic analysis for multi-processor execution replay.	MICRO	2009	DBLP DOI BibTeX RDF	multi-processor replay, shared-memory dependencies, SMT solver
1	Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das	Application-aware prioritization mechanisms for on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF	multi-core, packet scheduling, memory systems, arbitration, prioritization, on-chip networks
1	Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu	Improving cache lifetime reliability at ultra-low voltages.	MICRO	2009	DBLP DOI BibTeX RDF
1	Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz	Using a configurable processor generator for computer architecture prototyping.	MICRO	2009	DBLP DOI BibTeX RDF	computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design
1	Boris Grot, Stephen W. Keckler, Onur Mutlu	Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip.	MICRO	2009	DBLP DOI BibTeX RDF
1	Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser	Multiple clock and voltage domains for chip multi processors.	MICRO	2009	DBLP DOI BibTeX RDF	clock domains, voltage domain, power management, DVFS, chip multi processor
1	Hyunchul Park, Yongjun Park, Scott A. Mahlke	Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications.	MICRO	2009	DBLP DOI BibTeX RDF	programmable accelerator, virtualization, software pipelining

Publications at "MICRO"( http://dblp.L3S.de/Venues/MICRO )