Search results for "MICRO"

Hits ?▲	Authors	Title	Venue	Year	Link
1		45th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2012, Vancouver, BC, Canada, December 1-5, 2012	MICRO	2012	DBLP BibTeX RDF
1	Damien Hardy, Isidoros Sideris, Nikolas Ladas, Yiannakis Sazeides	The Performance Vulnerability of Architectural and Non-architectural Arrays to Permanent Faults.	MICRO	2012	DBLP DOI BibTeX RDF
1	Petar Radojkovic, Paul M. Carpenter, Miquel Moretó, Alex Ramírez, Francisco J. Cazorla	Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem.	MICRO	2012	DBLP DOI BibTeX RDF
1	Qingyuan Deng, David Meisner, Abhishek Bhattacharjee, Thomas F. Wenisch, Ricardo Bianchini	CoScale: Coordinating CPU and Memory System DVFS in Server Systems.	MICRO	2012	DBLP DOI BibTeX RDF
1	Akbar Sharifi, Emre Kultursay, Mahmut T. Kandemir, Chita R. Das	Addressing End-to-End Memory Access Latency in NoC-Based Multicores.	MICRO	2012	DBLP DOI BibTeX RDF
1	Youngtaek Kim, Lizy Kurian John, Sanjay Pant, Srilatha Manne, Michael J. Schulte, William Lloyd Bircher, Madhu S. Sibi Govindan	AUDIT: Stress Testing the Automatic Way.	MICRO	2012	DBLP DOI BibTeX RDF
1	Krishna T. Malladi, Ian Shaeffer, Liji Gopalakrishnan, David Lo, Benjamin C. Lee, Mark Horowitz	Rethinking DRAM Power Modes for Energy Proportionality.	MICRO	2012	DBLP DOI BibTeX RDF
1	Hadi Esmaeilzadeh, Adrian Sampson, Luis Ceze, Doug Burger	Neural Acceleration for General-Purpose Approximate Programs.	MICRO	2012	DBLP DOI BibTeX RDF
1	Mohammad Alisafaee	Spatiotemporal Coherence Tracking.	MICRO	2012	DBLP DOI BibTeX RDF
1	Andrew Lukefahr, Shruti Padmanabha, Reetuparna Das, Faissal M. Sleiman, Ronald G. Dreslinski, Thomas F. Wenisch, Scott A. Mahlke	Composite Cores: Pushing Heterogeneity Into a Core.	MICRO	2012	DBLP DOI BibTeX RDF
1	Niladrish Chatterjee, Manjunath Shevgoor, Rajeev Balasubramonian, Al Davis, Zhen Fang, Ramesh Illikkal, Ravi Iyer	Leveraging Heterogeneity in DRAM Main Memories to Accelerate Critical Word Access.	MICRO	2012	DBLP DOI BibTeX RDF
1	Alain Ketterlin, Philippe Clauss	Profiling Data-Dependence to Assist Parallelization: Framework, Scope, and Optimization.	MICRO	2012	DBLP DOI BibTeX RDF
1	Snehasish Kumar, Hongzhou Zhao, Arrvindh Shriraman, Eric Matthews, Sandhya Dwarkadas, Lesley Shannon	Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy.	MICRO	2012	DBLP DOI BibTeX RDF
1	Lizhong Chen, Timothy Mark Pinkston	NoRD: Node-Router Decoupling for Effective Power-gating of On-Chip Routers.	MICRO	2012	DBLP DOI BibTeX RDF
1	Daniel Wong 0001, Murali Annavaram	KnightShift: Scaling the Energy Proportionality Wall through Server-Level Heterogeneity.	MICRO	2012	DBLP DOI BibTeX RDF
1	Nam Duong, Dali Zhao, Taesu Kim, Rosario Cammarota, Mateo Valero, Alexander V. Veidenbaum	Improving Cache Management Policies Using Dynamic Reuse Distances.	MICRO	2012	DBLP DOI BibTeX RDF
1	Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt	Cache-Conscious Wavefront Scheduling.	MICRO	2012	DBLP DOI BibTeX RDF
1	Cheng Wang, Youfeng Wu, Hongbo Rong, Hyunchul Park	SMARQ: Software-Managed Alias Register Queue for Dynamic Optimizations.	MICRO	2012	DBLP DOI BibTeX RDF
1	Rustam Miftakhutdinov, Eiman Ebrahimi, Yale N. Patt	Predicting Performance Impact of DVFS for Realistic Memory Systems.	MICRO	2012	DBLP DOI BibTeX RDF
1	Rami Sheikh, James Tuck, Eric Rotenberg	Control-Flow Decoupling.	MICRO	2012	DBLP DOI BibTeX RDF
1	Haicheng Wu, Gregory Frederick Diamos, Srihari Cadambi, Sudhakar Yalamanchili	Kernel Weaver: Automatically Fusing Database Primitives for Efficient GPU Computation.	MICRO	2012	DBLP DOI BibTeX RDF
1	Christian Jacobi, Timothy J. Slegel, Dan F. Greiner	Transactional Memory Architecture and Implementation for IBM System Z.	MICRO	2012	DBLP DOI BibTeX RDF
1	Jan van Lunteren, Christoph Hagleitner, Timothy Heil, Giora Biran, Uzi Shvadron, Kubilay Atasu	Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator.	MICRO	2012	DBLP DOI BibTeX RDF
1	Khubaib, M. Aater Suleman, Milad Hashemi, Chris Wilkerson, Yale N. Patt	MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP.	MICRO	2012	DBLP DOI BibTeX RDF
1	Jaewoong Sim, Gabriel H. Loh, Hyesoon Kim, Mike O'Connor, Mithuna Thottethodi	A Mostly-Clean DRAM Cache for Effective Hit Speculation and Self-Balancing Dispatch.	MICRO	2012	DBLP DOI BibTeX RDF
1	Ramon Bertran, Alper Buyuktosunoglu, Meeta Sharma Gupta, Marc González, Pradip Bose	Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks.	MICRO	2012	DBLP DOI BibTeX RDF
1	Yongjun Park, Jason Jong Kyu Park, Hyunchul Park, Scott A. Mahlke	Libra: Tailoring SIMD Execution Using Heterogeneous Hardware and Dynamic Configurability.	MICRO	2012	DBLP DOI BibTeX RDF
1	Timothy Hayes, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Mateo Valero	Vector Extensions for Decision Support DBMS Acceleration.	MICRO	2012	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi, Gabe H. Loh	Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design.	MICRO	2012	DBLP DOI BibTeX RDF
1	Socrates Demetriades, Sangyeun Cho	Predicting Coherence Communication by Tracking Synchronization Points at Run Time.	MICRO	2012	DBLP DOI BibTeX RDF
1	Lei Jiang, Youtao Zhang, Bruce R. Childers, Jun Yang 0002	FPB: Fine-grained Power Budgeting to Improve Write Throughput of Multi-level Cell Phase Change Memory.	MICRO	2012	DBLP DOI BibTeX RDF
1	Hyeran Jeon, Murali Annavaram	Warped-DMR: Light-weight Error Detection for GPGPU.	MICRO	2012	DBLP DOI BibTeX RDF
1	Abdullah Muzahid, Shanxiang Qi, Josep Torrellas	Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically.	MICRO	2012	DBLP DOI BibTeX RDF
1	Randy Morris, Avinash Karanth Kodi, Ahmed Louri	Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance.	MICRO	2012	DBLP DOI BibTeX RDF
1	Andreas Prodromou, Andreas Panteli, Chrysostomos Nicopoulos, Yiannakis Sazeides	NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures.	MICRO	2012	DBLP DOI BibTeX RDF
1	Pejman Lotfi-Kamran, Boris Grot, Babak Falsafi	NOC-Out: Microarchitecting a Scale-Out Processor.	MICRO	2012	DBLP DOI BibTeX RDF
1	Islam Atta, Pinar Tözün, Anastasia Ailamaki, Andreas Moshovos	SLICC: Self-Assembly of Instruction Cache Collectives for OLTP Workloads.	MICRO	2012	DBLP DOI BibTeX RDF
1	Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally	Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor.	MICRO	2012	DBLP DOI BibTeX RDF
1	Binh Pham, Viswanathan Vaidyanathan, Aamer Jaleel, Abhishek Bhattacharjee	CoLT: Coalesced Large-Reach TLBs.	MICRO	2012	DBLP DOI BibTeX RDF
1	Wei Huang, Charles Lefurgy, William Kuk, Alper Buyuktosunoglu, Michael S. Floyd, Karthick Rajamani, Malcolm Allen-Ware, Bishop Brock	Accurate Fine-Grained Processor Power Proxies.	MICRO	2012	DBLP DOI BibTeX RDF
1	Weidan Wu, Benjamin C. Lee	Inferred Models for Dynamic and Sparse Hardware-Software Spaces.	MICRO	2012	DBLP DOI BibTeX RDF
1	Nikolas Ioannou, Marcelo Cintra	Complementing user-level coarse-grain parallelism with implicit speculative parallelism.	MICRO	2011	DBLP DOI BibTeX RDF
1	Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter	Active management of timing guardband to save energy in POWER7.	MICRO	2011	DBLP DOI BibTeX RDF
1	Konstantinos Aisopos, Li-Shiuan Peh	A systematic methodology to develop resilient cache coherence protocols.	MICRO	2011	DBLP DOI BibTeX RDF
1	Mitchell Hayenga, Mikko H. Lipasti	The NoX router.	MICRO	2011	DBLP DOI BibTeX RDF
1	Jason Mars, Lingjia Tang, Robert Hundt, Kevin Skadron, Mary Lou Soffa	Bubble-Up: increasing utilization in modern warehouse scale computers via sensible co-locations.	MICRO	2011	DBLP DOI BibTeX RDF
1	Ganesh Venkatesh, Jack Sampson, Nathan Goulding-Hotta, Sravanthi Kota Venkata, Michael Bedford Taylor, Steven Swanson	QsCores: trading dark silicon for scalable energy efficiency with quasi-specific cores.	MICRO	2011	DBLP DOI BibTeX RDF
1	Carole-Jean Wu, Aamer Jaleel, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer	PACMan: prefetch-aware cache management for high performance caching.	MICRO	2011	DBLP DOI BibTeX RDF
1	Moinuddin K. Qureshi	Pay-As-You-Go: low-overhead hard-error correction for phase change memories.	MICRO	2011	DBLP DOI BibTeX RDF
1	Yuanrui Zhang, Wei Ding, Mahmut T. Kandemir, Jun Liu, Ohyoung Jang	A data layout optimization framework for NUCA-based multicores.	MICRO	2011	DBLP DOI BibTeX RDF
1	Yan Pan, John Kim, Gokhan Memik	FeatherWeight: low-cost optical arbitration with QoS support.	MICRO	2011	DBLP DOI BibTeX RDF
1	Mark Gebhart, Stephen W. Keckler, William J. Dally	A compile-time managed multi-level register file hierarchy.	MICRO	2011	DBLP DOI BibTeX RDF
1	Sheng Li, Kevin T. Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi	System-level integrated server architectures for scale-out datacenters.	MICRO	2011	DBLP DOI BibTeX RDF
1	Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott A. Mahlke, David I. August	Encore: low-cost, fine-grained transient fault recovery.	MICRO	2011	DBLP DOI BibTeX RDF
1	Qing Guo, Xiaochen Guo, Yuxin Bai, Engin Ipek	A resistive TCAM accelerator for data-intensive computing.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gregory Frederick Diamos, Benjamin Ashbaugh, Subramaniam Maiyuran, Andrew Kerr, Haicheng Wu, Sudhakar Yalamanchili	SIMD re-convergence at thread frontiers.	MICRO	2011	DBLP DOI BibTeX RDF
1	Jing Xin, Russ Joseph	Identifying and predicting timing-critical instructions to boost timing speculation.	MICRO	2011	DBLP DOI BibTeX RDF
1	Carlo Galuzzi, Luigi Carro, Andreas Moshovos, Milos Prvulovic (eds.)	44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, 3-7 December 2011, Porto Alegre, Brazil	MICRO	2011	DBLP BibTeX RDF
1	André Seznec	A new case for the TAGE branch predictor.	MICRO	2011	DBLP DOI BibTeX RDF
1	George Michelogiannakis, Nan Jiang, Daniel U. Becker, William J. Dally	Packet chaining: efficient single-cycle allocation for on-chip networks.	MICRO	2011	DBLP DOI BibTeX RDF
1	Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt	Improving GPU performance via large warps and two-level warp scheduling.	MICRO	2011	DBLP DOI BibTeX RDF
1	Marc de Kruijf, Karthikeyan Sankaralingam	Idempotent processor architecture.	MICRO	2011	DBLP DOI BibTeX RDF
1	Seongwook Jin, Jeongseob Ahn, Sanghoon Cha, Jaehyuk Huh	Architectural support for secure virtualization under a vulnerable hypervisor.	MICRO	2011	DBLP DOI BibTeX RDF
1	Andrew Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger	Preventing PCM banks from seizing too much power.	MICRO	2011	DBLP DOI BibTeX RDF
1	Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke, David I. August	Bundled execution of recurring traces for energy-efficient general purpose processing.	MICRO	2011	DBLP DOI BibTeX RDF
1	Michael Ferdman, Cansu Kaynak, Babak Falsafi	Proactive instruction fetch.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gabriel H. Loh	A register-file approach for row buffer caches in die-stacked DRAMs.	MICRO	2011	DBLP DOI BibTeX RDF
1	Christopher Nitta, Matthew K. Farrens, Venkatesh Akella	Resilient microring resonator based photonic networks.	MICRO	2011	DBLP DOI BibTeX RDF
1	Jesse G. Beu, Michel C. Rosier, Thomas M. Conte	Manager-client pairing: a framework for implementing coherence hierarchies.	MICRO	2011	DBLP DOI BibTeX RDF
1	Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González	Accelerating microprocessor silicon validation by exposing ISA diversity.	MICRO	2011	DBLP DOI BibTeX RDF
1	Soontae Kim, Jongmin Lee 0002, Jesung Kim, Seokin Hong	Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gilles Pokam, Cristiano Pereira, Shiliang Hu, Ali-Reza Adl-Tabatabai, Justin Emile Gottschlich, Jungwoo Ha, Youfeng Wu	CoreRacer: a practical memory race recorder for multicore x86 TSO processors.	MICRO	2011	DBLP DOI BibTeX RDF
1	Tushar Krishna, Li-Shiuan Peh, Bradford M. Beckmann, Steven K. Reinhardt	Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication.	MICRO	2011	DBLP DOI BibTeX RDF
1	Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John	Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era.	MICRO	2011	DBLP DOI BibTeX RDF
1	Vignyan Reddy Kothinti Naresh, David J. Palframan, Mikko H. Lipasti	CRAM: coded registers for amplified multiporting.	MICRO	2011	DBLP DOI BibTeX RDF
1	Ritesh Parikh, Valeria Bertacco	Formally enhanced runtime verification to ensure NoC functional correctness.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gabriel H. Loh, Mark D. Hill	Efficiently enabling conventional block sizes for very large die-stacked DRAM caches.	MICRO	2011	DBLP DOI BibTeX RDF
1	Carole-Jean Wu, Aamer Jaleel, William Hasenplaugh, Margaret Martonosi, Simon C. Steely Jr., Joel S. Emer	SHiP: signature-based hit predictor for high performance caching.	MICRO	2011	DBLP DOI BibTeX RDF
1	Wilson W. L. Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt	Hardware transactional memory for GPU architectures.	MICRO	2011	DBLP DOI BibTeX RDF
1	Ahmed H. Abdel-Gawad, Mithuna Thottethodi	TransCom: transforming stream communication for load balance and efficiency in networks-on-chip.	MICRO	2011	DBLP DOI BibTeX RDF
1	Gagan Gupta, Gurindar S. Sohi	Dataflow execution of sequential imperative programs on multicore architectures.	MICRO	2011	DBLP DOI BibTeX RDF
1	Zhenyu Sun, Xiuyuan Bi, Hai Helen Li, Weng-Fai Wong, Zhong-Liang Ong, Xiaochun Zhu, Wenqing Wu	Multi retention level STT-RAM cache designs with a dynamic refresh scheme.	MICRO	2011	DBLP DOI BibTeX RDF
1	Jiaqi Zhang, Weiwei Xiong, Yang Liu, Soyeon Park, Yuanyuan Zhou, Zhiqiang Ma	ATDetector: improving the accuracy of a commercial data race detector by identifying address transfer.	MICRO	2011	DBLP DOI BibTeX RDF
1	Ryan Cochran, Can Hankendi, Ayse Kivilcim Coskun, Sherief Reda	Pack & Cap: adaptive DVFS and thread packing under power caps.	MICRO	2011	DBLP DOI BibTeX RDF
1	Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut T. Kandemir, Thomas Moscibroda	Reducing memory interference in multicore systems via application-aware memory channel partitioning.	MICRO	2011	DBLP DOI BibTeX RDF
1	Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt	Parallel application memory scheduling.	MICRO	2011	DBLP DOI BibTeX RDF
1	Adrian Nistor, Darko Marinov, Josep Torrellas	InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, Richard W. Vuduc	Many-Thread Aware Prefetching Mechanisms for GPGPU Applications.	MICRO	2010	DBLP DOI BibTeX RDF
1	Abdullah Muzahid, Norimasa Otsuki, Josep Torrellas	AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection.	MICRO	2010	DBLP DOI BibTeX RDF
1	Hanjun Kim, Arun Raman, Feng Liu, Jae W. Lee, David I. August	Scalable Speculative Parallelization on Commodity Clusters.	MICRO	2010	DBLP DOI BibTeX RDF
1	Utku Aydonat, Tarek S. Abdelrahman	Hardware Support for Relaxed Concurrency Control in Transactional Memory.	MICRO	2010	DBLP DOI BibTeX RDF
1	Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero	Task Superscalar: An Out-of-Order Task Pipeline.	MICRO	2010	DBLP DOI BibTeX RDF
1	Timothy N. Miller, Renji Thomas, James Dinan, Bruce M. Adcock, Radu Teodorescu	Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches.	MICRO	2010	DBLP DOI BibTeX RDF
1	Rajkishore Barik, Jisheng Zhao, Vivek Sarkar	Efficient Selection of Vector Instructions Using Dynamic Programming.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong 0001, Murali Annavaram, Michel Dubois	Adaptive and Speculative Slack Simulations of CMPs on CMPs.	MICRO	2010	DBLP DOI BibTeX RDF
1	Adrian M. Caulfield, Arup De, Joel Coburn, Todor I. Mollow, Rajesh K. Gupta, Steven Swanson	Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories.	MICRO	2010	DBLP DOI BibTeX RDF
1		43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA	MICRO	2010	DBLP BibTeX RDF
1	Minseon Ahn, Eun Jung Kim 0001	Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jae-Woong Chung, Luke Yen, Stephan Diestelhorst, Martin Pohlack, Michael Hohmuth, David Christie, Dan Grossman	ASF: AMD64 Extension for Lock-Free Data Structures and Transactional Memory.	MICRO	2010	DBLP DOI BibTeX RDF
1	Samira Manabi Khan, Yingying Tian, Daniel A. Jiménez	Sampling Dead Block Prediction for Last-Level Caches.	MICRO	2010	DBLP DOI BibTeX RDF

Publications at "MICRO"( http://dblp.L3S.de/Venues/MICRO )