Search results for "MP-SoC"

Found 8 publication records. Showing 8 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Ahsan Shabbir, Sander Stuijk, Akash Kumar, Bart D. Theelen, Bart Mesman, Henk Corporaal	A predictable communication assist.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	fpga's, communication, predictable, dma, ca, mp-soc
1	Sílvio R. F. de Fernandes, Bruno Cruz de Oliveira, Ivan Saraiva Silva	Using NoC routers as processing elements.	SBCCI	2009	DBLP DOI BibTeX RDF	SoC, system-on-chip, network-on-chip, routing algorithm, NoC, MP-SoC
1	Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini	SHAPES: : a tiled scalable software hardware architecture platform for embedded systems.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	MP-SOC, distributed network processors, hardware dependent software, network of processes, tiled parallel architectures, simulation, scheduling, embedded systems, VLIW, RISC, model based design, binding, retargetable compiler, application mapping
1	Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel	Retargetable generation of TLM bus interfaces for MP-SoC platforms.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	simulation, SystemC, architecture exploration, TLM, retargetability, MP-SoC
1	Partha Pratim Pande, Cristian Grecu, Michael Jones, André Ivanov, Resve A. Saleh	Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	system-on-chip, Network-on-chip, interconnect architecture, MP-SoC, infrastructure IP
1	Tim Kogel, Heinrich Meyr	Heterogeneous MP-SoC: the solution to energy-efficient signal processing.	DAC	2004	DBLP DOI BibTeX RDF	energy efficiency, network-on-chip, signal processing, design space exploration, MP-SoC
1	Vincent Nollet, Théodore Marescaux, Diederik Verkest, Jean-Yves Mignolet, Serge Vernalde	Operating-system controlled network on chip.	DAC	2004	DBLP DOI BibTeX RDF	operating system, network on chip, MP-SoC
1	Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh	Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	BFT, scalability, pipelining, bus, MP-SoC

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