Search results for "MPSoC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Yiannis Iosifidis, Arindam Mallik, Stylianos Mamagkakis, Eddy de Greef, Alexandros Bartzas, Dimitrios Soudris, Francky Catthoor	A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms.	DAC	2010	DBLP DOI BibTeX RDF	embedded systems, MPSoC, memory optimization
3	Bjorn De Sutter, Diederik Verkest, Erik Brockmeyer, Eric Delfosse, Arnout Vandecappelle, Jean-Yves Mignolet	Design and Tool Flow of Multimedia MPSoC Platforms.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Tool flow, Multimedia, Parallelization, Predictability, MPSoC
3	Patrice Gerin, Mian Muhammad Hamayun, Frédéric Pétrot	Native MPSoC co-simulation environment for software performance estimation.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	code annotation, MPSoC, system simulation, cross-compilation
3	Anders Sejer Tranberg-Hansen, Jan Madsen	A compositional modelling framework for exploring MPSoC systems.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	MPSoC, system level design, performance estimation
3	Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	A high-level virtual platform for early MPSoC software development.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	simulation, parallel programming, software, embedded, MPSoC, system level design, virtual platform
3	Qiwei Zhang, André B. J. Kokkeler, Gerard J. M. Smit	Cognitive Radio Design on an MPSoC Reconfigurable Platform.	MONET	2008	DBLP DOI BibTeX RDF	task transaction level interface, sparse FFT, OFDM, cognitive radio, design method, MPSoC
3	Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda	MAPS: an integrated framework for MPSoC application parallelization.	DAC	2008	DBLP DOI BibTeX RDF	MPSoC programming, parallelization, software, embedded
3	Eric Cheung, Harry Hsieh, Felice Balarin	Software optimization for MPSoC: a mpeg-2 decoder case study.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	mpsoc, software optimization
3	Gustavo Girão, Bruno Cruz de Oliveira, Rodrigo Soares, Ivan Saraiva Silva	Cache coherency communication cost in a NoC-based MPSoC platform.	SBCCI	2007	DBLP DOI BibTeX RDF	cache coherence, MPSoC, NoC, directory
3	Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar	Adaptive Sampling for Efficient MPSoC Architecture Simulation.	MASCOTS	2007	DBLP DOI BibTeX RDF	Simulation, Sampling, MPSoC, Acceleration
3	Ines Viskic, Samar Abdi, Daniel D. Gajski	Automatic generation of embedded communication SW for heterogeneous MPSoC platforms.	LCTES	2007	DBLP DOI BibTeX RDF	custom communication SW, pin/cycle accurate models, MPSoC, system level design, transaction level models, platform based design, automatic synthesis, on-chip communication
3	Pramod Chandraiah, Rainer Dömer	Pointer re-coding for creating definitive MPSoC models.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	re-coding, MPSoC, pointers, system specification
3	Julien Bernard, Jean-Louis Roch, Serge De Paoli, Miguel Santana	Adaptive Encoding of Multimedia Streams on MPSoC.	International Conference on Computational Science	2006	DBLP DOI BibTeX RDF	scheduling, MPSoC, work-stealing
3	Ozcan Ozturk, Mahmut T. Kandemir, Seung Woo Son, Mustafa Karaköy	Selective code/data migration for reducing communication energy in embedded MpSoC architectures.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	energy, migration, MPSoC
3	Grant Martin	Overview of the MPSoC design challenge.	DAC	2006	DBLP DOI BibTeX RDF	MPSoC, system-level design, multi-processor system-on-chip
3	Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitra	Integrated scratchpad memory optimization and task scheduling for MPSoC architectures.	CASES	2006	DBLP DOI BibTeX RDF	scheduling, MPSoC, scratchpad memory, task mapping
3	Hong Yue, Zhiying Wang, Kui Dai	A Heterogeneous Embedded MPSoC for Multimedia Applications.	HPCC	2006	DBLP DOI BibTeX RDF	Transport Triggered Architecture, DSP, Embedded Processor, Heterogeneous MPSoC
3	Ozcan Ozturk, Mahmut T. Kandemir, Mary Jane Irwin	Using data compression in an MPSoC architecture for improving performance.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	compression, MPSoC
3	Slo-Li Chu	POERS: A Performance-Oriented Energy Reduction Scheduling Technique for a High-Performance MPSoC Architecture.	ICPADS	2005	DBLP DOI BibTeX RDF	POERS, SAGE II, MPSoC, Processor-in-Memory, Energy Reduction
3	Feihui Li, Mahmut T. Kandemir	Locality-conscious workload assignment for array-based computations in MPSOC architectures.	DAC	2005	DBLP DOI BibTeX RDF	MPSoC, data locality
2	Francesco Paterna, Andrea Acquaviva, Alberto Caprara, Francesco Papariello, Giuseppe Desoli, Luca Benini	Variability-tolerant run-time workload allocation for MPSoC energy minimization under real-time constraints.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	real-time, variability, mpsoc, energy minimization
2	Zheng Liu, Jueping Cai, Ming Du, Lei Yao, Zan Li	Hybrid Communication Reconfigurable Network on Chip for MPSoC.	AINA	2010	DBLP DOI BibTeX RDF	HCR-NoC, low power, interconnection, MPSoC
2	Nicolas Ventroux, Alexandre Guerre, Tanguy Sassolas, L. Moutaoukil, Guillaume Blanc, Charly Bechara, Raphaël David	SESAM: An MPSoC Simulation Environment for Dynamic Application Processing.	CIT	2010	DBLP DOI BibTeX RDF	SESAM, simulation, modeling, multiprocessor, dynamic, exploration, SystemC, MPSoC
2	Ines Viskic, Lochi Yu, Daniel Gajski	Design exploration and automatic generation of MPSoC platform TLMs from Kahn Process Network applications.	LCTES	2010	DBLP DOI BibTeX RDF	kahn process, transaction level model, automatic generation, process network, process mapping
2	Diana Göhringer, Michael Hübner, Michael Benz, Jürgen Becker	A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	designflow, toolchain, fpga, partitioning, reconfigurable computing, mpsoc, hardware/software co-design
2	Narasinga Rao Miniskar, Elena Hammari, Satyakiran Munaga, Stylianos Mamagkakis, Per Gunnar Kjeldsberg, Francky Catthoor	Scenario Based Mapping of Dynamic Applications on MPSoC: A 3D Graphics Case Study.	SAMOS	2009	DBLP DOI BibTeX RDF
2	Hritam Dutta, Frank Hannig, Jürgen Teich	Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis.	ARCS	2009	DBLP DOI BibTeX RDF
2	Francesco Zanini, David Atienza, Giovanni De Micheli	A control theory approach for thermal balancing of MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Eric Cheung, Harry Hsieh, Felice Balarin	Fast and accurate performance simulation of embedded software for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Katalin Popovici, Ahmed Amine Jerraya	Flexible and abstract communication and interconnect modeling for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Hao Shen, Frédéric Pétrot	Novel task migration framework on configurable heterogeneous MPSoC platforms.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	HaNeul Chon, Taewhan Kim	Timing variation-aware task scheduling and binding for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Eric Cheung, Harry Hsieh, Felice Balarin	Partial order method for timed simulation of system-level MPSoC designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
2	Deepak Gangadharan, Samarjit Chakraborty, Roger Zimmermann	Fast model-based test case classification for performance analysis of multimedia MPSoC platforms.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	multimedia, workload, video classification
2	Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda, Toshio Isomura, Kazuo Satou	Trace-driven workload simulation method for Multiprocessor System-On-Chips.	DAC	2009	DBLP DOI BibTeX RDF	MPSoC architecture exploration, simulation, performance estimation, workload model
2	Felipe Klein, Alexandro Baldassin, Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo	On the energy-efficiency of software transactional memory.	SBCCI	2009	DBLP DOI BibTeX RDF	low power design, transactional memory, multi-core, MPSoC
2	Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen	Evaluating SoC Network Performance in MPEG-4 Encoder.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	FPGA multiprocessor, Multiprocessor, System-on-chip, Network-on-chip, MPEG-4, MPSoC, On-chip interconnection
2	Ilya Issenin, Nikil Dutt	Using FORAY Models to Enable MPSoC Memory Optimizations.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	FORAY model, affine index expressions, Embedded systems, MPSoC, memory optimizations, scratch pad memory
2	Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Michela Milano, Luca Benini	A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	scheduling, Integer Programming, Constraint Programming, MPSoCs, allocation
2	Seongnam Kwon, Yongjoo Kim, Woo-Chul Jeun, Soonhoi Ha, Yunheung Paek	A retargetable parallel-programming framework for MPSoC.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	parallel-programming, design-space exploration, Embedded software, multiprocessor system on chip, software generation
2	Pramod Chandraiah, Rainer Dömer	Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen	A Reactive and Cycle-True IP Emulator for MPSoC Exploration.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Wayne Wolf, Ahmed Amine Jerraya, Grant Martin	Multiprocessor System-on-Chip (MPSoC) Technology.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
2	Zhenyu (Peter) Gu, Changyun Zhu, Li Shang, Robert P. Dick	Application-Specific MPSoC Reliability Optimization.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
2	Ahsan Shabbir, Akash Kumar, Bart Mesman, Henk Corporaal	Enabling MPSoC Design Space Exploration on FPGAs.	IMTIC	2008	DBLP DOI BibTeX RDF	FPGAs, MPSoC, FIFO, FSL
2	Kimon Karras, Elias S. Manolakos	An embedded dynamically self-reconfigurable Master-Slaves MPSoC architecture.	FPL	2008	DBLP DOI BibTeX RDF
2	Joachim Falk, Joachim Keinert, Christian Haubelt, Jürgen Teich, Shuvra S. Bhattacharyya	A generalized static data flow clustering algorithm for mpsoc scheduling of multimedia applications.	EMSOFT	2008	DBLP DOI BibTeX RDF	actor-oriented design, mpsoc scheduling, software synthesis
2	Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa	A Modular Approach to Model Heterogeneous MPSoC at Cycle Level.	DSD	2008	DBLP DOI BibTeX RDF
2	Feng Wang 0004, Yuan Xie	Embedded Multi-Processor System-on-chip (MPSoC) design considering process variations.	IPDPS	2008	DBLP DOI BibTeX RDF
2	Luca Benini, Davide Bertozzi, Michela Milano	Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming.	ICLP	2008	DBLP DOI BibTeX RDF
2	Jehangir Khan, Smaïl Niar, Atika Rivenq, Yassin Elhillali, Jean-Luc Dekeyser	An MPSoC architecture for the Multiple Target Tracking application in driver assistant system.	ASAP	2008	DBLP DOI BibTeX RDF
2	Anders Sejer Tranberg-Hansen, Jan Madsen, Bjørn Sand Jensen	A service based estimation method for MPSoC performance modelling.	SIES	2008	DBLP DOI BibTeX RDF
2	Hao Shen, Frédéric Pétrot	MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Patrice Gerin, Xavier Guerin, Frédéric Pétrot	Efficient Implementation of Native Software Simulation for MPSoC.	DATE	2008	DBLP DOI BibTeX RDF
2	Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina	xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures.	PDP	2008	DBLP DOI BibTeX RDF	NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques
2	Bart D. Theelen	Performance Model Generation for MPSoC Design-Space Exploration.	QEST	2008	DBLP DOI BibTeX RDF
2	Zai Jian Jia, Tomás Bautista, Antonio Núñez, Cayetano Guerra, Mario Hernández	Design Space Exploration and Performance Analysis for the Modular Design of CVS in a Heterogeneous MPSoC.	ReConFig	2008	DBLP DOI BibTeX RDF	Design space exploration, platform-based design, tracking algorithm, heterogeneous MPSoC
2	Sung-Kwan Ku, Han-Sam Jung, Ki-Seok Chung	A unified power measurement and management platform for pipelined MPSoC executions.	SoCC	2008	DBLP DOI BibTeX RDF
2	Frank E. B. Ophelders, Samarjit Chakraborty, Henk Corporaal	Intra- and inter-processor hybrid performance modeling for MPSoC architectures.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	simulation, performance analysis, system-on-chip
2	Krutartha Patel, Sri Parameswaran	LOCS: a low overhead profiler-driven design flow for security of MPSoCs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	tensilica, architecture, mpsoc, execution profile, code injection
2	Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Multiprocessor performance estimation using hybrid simulation.	DAC	2008	DBLP DOI BibTeX RDF	HySim, address recovery, cross replay, MPSoC, performance estimation, cache simulation, hybrid simulation
2	Eshel Haritan, Toshihiro Hattori, Hiroyuki Yagi, Pierre G. Paulin, Wayne Wolf, Achim Nohl, Drew Wingard, Mike Muller	Multicore design is the challenge! what is the solution?	DAC	2008	DBLP DOI BibTeX RDF	heterogeneous/homogenous multicore, symmetric/asymmetric multicore, multiprocessors, interconnect, multi-core, MPSoC, programming model, virtual prototyping, ESL, virtual platforms
2	Minyoung Kim, Sudarshan Banerjee, Nikil Dutt, Nalini Venkatasubramanian	Energy-aware cosynthesis of real-time multimedia applications on MPSoCs using heterogeneous scheduling policies.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	cosynthesis, energy, Real-time scheduling, MPSoC
2	Lobna Kriaa, Aimen Bouchhima, Marius Gligor, Anne-Marie Fouillart, Frédéric Pétrot, Ahmed Amine Jerraya	Parallel Programming of Multi-processor SoC: A HW-SW Interface Perspective.	International Journal of Parallel Programming	2008	DBLP DOI BibTeX RDF	HW/SW interfaces, Programming models, heterogeneous MPSoC
2	Grant Martin	Multi-Processor SoC-Based Design Methodologies Using Configurable and Extensible Processors.	Signal Processing Systems	2008	DBLP DOI BibTeX RDF	MPSoC, programming models, dataflow, instruction-set extension, multiprocessor system-on-chip, configurable processor, electronic system-level design
2	Mirko Loghi, Luca Benini, Massimo Poncino	Power macromodeling of MPSoC message passing primitives.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	multiprocessor, system-on-chip, macromodeling, Communication primitives
2	Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara, Hasan Khalifeh, Mazen Hajjar, Rustam Nabiev, Sven Jonsson	Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology.	T. HiPEAC	2007	DBLP DOI BibTeX RDF	HW/SW, hardware space exploration, embedded system design, Multiprocessor System-on-Chip, real-time analysis, electrocardiogram algorithms
2	Youcef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre G. Paulin	MPSoC memory optimization using program transformation.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	embedded systems, data cache, Data locality, compiler transformations
2	Sudeep Pasricha, Nikil D. Dutt	A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	Youngmin Yi, Dohyung Kim, Soonhoi Ha	Fast and Accurate Cosimulation of MPSoC Using Trace-Driven Virtual Synchronization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
2	AbdelHalim Samahi, El-Bay Bourennane	Automated Integration and Communication Synthesis of Reconfigurable MPSoC Platform.	AHS	2007	DBLP DOI BibTeX RDF
2	Youssef Atat, Nacer-Eddine Zergainoh	Simulink-based MPSoC Design: New Approach to Bridge the Gap between Algorithm and Architecture Design.	ISVLSI	2007	DBLP DOI BibTeX RDF
2	Gilles Sassatelli, Nicolas Saint-Jean, Cristiane R. Woszezenki, Ismael Grehs, Fernando Gehm Moraes	Architectural Issues in Homogeneous NoC-Based MPSoC.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
2	Marcio F. da S. Oliveira, Eduardo Wenzel Brião, Francisco Assis M. do Nascimento, Flávio Rech Wagner	Model driven engineering for MPSOC design space exploration.	SBCCI	2007	DBLP DOI BibTeX RDF	model driven engineering, design space exploration, multi-processor system-on-chip
2	Jan Willem van den Brand, Marco Bekooij	Streaming consistency: a model for efficient MPSoC design.	DSD	2007	DBLP DOI BibTeX RDF
2	Youcef Bouchebaba, Bruno Lavigueur, Bruno Girodias, Gabriela Nicolescu, Pierre G. Paulin	MPSoC memory optimization for digital camera applications.	DSD	2007	DBLP DOI BibTeX RDF
2	Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis, Soo-Ik Chae, Ahmed Amine Jerraya	Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.	SCOPES	2007	DBLP DOI BibTeX RDF
2	Pramod Chandraiah, Rainer Dömer	Designer-Controlled Generation of Parallel and Flexible Heterogeneous MPSoC Specification.	DAC	2007	DBLP DOI BibTeX RDF
2	Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya	Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264.	DAC	2007	DBLP DOI BibTeX RDF
2	Katalin Popovici, Ahmed Amine Jerraya	Simulink based hardware-software codesign flow for heterogeneous MPSoC.	SCSC	2007	DBLP DOI BibTeX RDF	hardware-software gradual refinement, multimedia applications, abstraction levels
2	Youcef Bouchebaba, Essaid Bensoudane, Bruno Lavigueur, Pierre G. Paulin, Gabriela Nicolescu	Two-level tiling for MPSoC architecture.	ASAP	2007	DBLP DOI BibTeX RDF
2	Andrea Marongiu, Luca Benini, Mahmut T. Kandemir	Lightweight barrier-based parallelization support for non-cache-coherent MPSoC platforms.	CASES	2007	DBLP DOI BibTeX RDF	code parallelization, MPSoCs, barrier synchronization
2	Soonhoi Ha	Model-based Programming Environment of Embedded Software for MPSoC.	ASP-DAC	2007	DBLP DOI BibTeX RDF
2	Márcio Oyamada, Flávio Rech Wagner, Marius Bonaciu, Wander O. Cesário, Ahmed Amine Jerraya	Software Performance Estimation in MPSoC Design.	ASP-DAC	2007	DBLP DOI BibTeX RDF	cycle-accurate simulation model, software performance estimation, MPSoC design, software-dominated embedded systems, integrated methodology, bus-functional model, multiprocessor platform, MPEG4 encoder, neural networks, performance analysis, design space exploration, design validation
2	Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser	An MPSoC Performance Estimation Framework Using Transaction Level Modeling.	RTCSA	2007	DBLP DOI BibTeX RDF
2	Jason Schlessman, Mark Lodato, Burak Ozer, Wayne Wolf	Heterogeneous MPSoC Architectures for Embedded Computer Vision.	ICME	2007	DBLP DOI BibTeX RDF
2	Matthieu Briere, Bruno Girodias, Youcef Bouchebaba, Gabriela Nicolescu, Fabien Mieyeville, Frédéric Gaffiot, Ian O'Connor	System level assessment of an optical NoC in an MPSoC platform.	DATE	2007	DBLP DOI BibTeX RDF
2	Simone Medardoni, Martino Ruggiero, Davide Bertozzi, Luca Benini, Giovanni Strano, Carlo Pistritto	Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.	DATE	2007	DBLP DOI BibTeX RDF
2	Tianmiao Wang, Kai Sun, Hongxing Wei, Meng Wang, Zili Shao, Hui Liu	Interconnection Synthesis of MPSoC Architecture for Gamma Cameras.	EUC	2007	DBLP DOI BibTeX RDF
2	Vincent Nollet, D. Verkestt	A Quick Safari Through the MPSoC Run-Time Management Jungle.	ESTImedia	2007	DBLP DOI BibTeX RDF
2	Feng Wang 0004, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan	Variation-aware task allocation and scheduling for MPSoC.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Chengmo Yang, Alex Orailoglu	Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	multiprocessor task schedulihng, reconfiguration, adaptive execution
2	Salvatore Carta, Andrea Acquaviva, Pablo Garcia Del Valle, David Atienza, Giovanni De Micheli, Fernando Rincón, Luca Benini, Jose Manuel Mendias	Multi-processor operating system emulation framework with thermal feedback for systems-on-chip.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	thermal studies, FPGA, operating system, emulation, MPSoC
2	Salvatore Carta, Andrea Alimonda, Alessandro Pisano, Andrea Acquaviva, Luca Benini	A control theoretic approach to energy-efficient pipelined computation in MPSoCs.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	feedback-control techniques, parallel systems, MPSoC, DVFS
2	David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida	HW-SW emulation framework for temperature-aware design in MPSoCs.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Thermal-aware design, FPGA, emulation, MPSoC, temperature
2	Yuan Xie, Wei-Lun Hung	Temperature-Aware Task Allocation and Scheduling for Embedded Multiprocessor Systems-on-Chip (MPSoC) Design.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	thermal-aware design, scheduling, embedded system design, system-on-chip design
2	Heikki Kariniemi, Jari Nurmi	On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips.	FPL	2006	DBLP DOI BibTeX RDF
2	Ana Lucia Varbanescu, Henk J. Sips, Arjan J. C. van Gemund	PAM-SoC: A Toolchain for Predicting MPSoC Performance.	Euro-Par	2006	DBLP DOI BibTeX RDF
2	Balal Ahmad, Ahmet T. Erdogan, Sami Khawam	Architecture of a Dynamically Reconfigurable NoC for Adaptive Reconfigurable MPSoC.	AHS	2006	DBLP DOI BibTeX RDF
2	Yuriy Sheynin, Elena Suvorova, Felix Shutenko	Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level Design.	ISVLSI	2006	DBLP DOI BibTeX RDF