Search results for "MTCMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Hassan Hassan, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
3	Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang	A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	DSTN, low power, MTCMOS, sleep transistor
3	Hanif Fatemi, Behnam Amelifard, Massoud Pedram	Power optimal MTCMOS repeater insertion for global buses.	ISLPED	2007	DBLP DOI BibTeX RDF	MTCMOS circuits, low-power design, buffer insertion
3	Chanseok Hwang, Peng Rong, Massoud Pedram	Sleep transistor distribution in row-based MTCMOS designs.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage minimization, placement, MTCMOS
3	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Charge recycling in MTCMOS circuits: concept and analysis.	DAC	2006	DBLP DOI BibTeX RDF	low power design, MTCMOS, charge recycling
3	Naoaki Ohkubo, Kimiyoshi Usami	Delay modeling and static timing analysis for MTCMOS circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF	interpolation., selective-MT, delay, leakage power, static timing analysis, MTCMOS
3	Benton H. Calhoun, Frank Honoré, Anantha Chandrakasan	Design methodology for fine-grained leakage control in MTCMOS.	ISLPED	2003	DBLP DOI BibTeX RDF	fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS
3	Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong	An MTCMOS design methodology and its application to mobile computing.	ISLPED	2003	DBLP DOI BibTeX RDF	CPFF, low power, leakage current, CCS, MTCMOS
2	Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di	Glitch-free design for multi-threshold CMOS NCL circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	asynchronous circuit, mtcmos, glitch, threshold gate, null convention logic
2	Charbel J. Akl, Magdy A. Bayoumi	Self-Sleep Buffer for Distributed MTCMOS Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
2	Zhiyu Liu, Volkan Kursun	Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS.	ISQED	2007	DBLP DOI BibTeX RDF	Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling
2	Zhiyu Liu, Volkan Kursun	Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions.	ISCAS	2007	DBLP DOI BibTeX RDF
2	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Sizing and placement of charge recycling transistors in MTCMOS circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
2	Chanseok Hwang, Chang Woo Kang, Massoud Pedram	Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs.	ISQED	2006	DBLP DOI BibTeX RDF
2	Saihua Lin, Hongli Gao, Huazhong Yang	Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS.	PATMOS	2006	DBLP DOI BibTeX RDF
2	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Low-power fanout optimization using MTCMOS and multi-Vt techniques.	ISLPED	2006	DBLP DOI BibTeX RDF	buffer chain, fanout tree, low-power design, fanout optimization
2	Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang	High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.	VLSI Design	2006	DBLP DOI BibTeX RDF
2	B. Chung, J. B. Kuo	Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Xin Zhao, Yici Cai, Qiang Zhou, Xianlong Hong	A novel low-power physical design methodology for MTCMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
2	Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka	Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.	ISQED	2005	DBLP DOI BibTeX RDF
2	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Low-overhead state-retaining elements for low-leakage MTCMOS design.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	MTCMOS design, state-retention, leakage power
2	Azadeh Davoodi, Ankur Srivastava	Wake-up protocols for controlling current surges in MTCMOS-based technology.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu	Functionality directed clustering for low power MTCMOS design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
2	Ramaprasath Vilangudipitchai, Poras T. Balsara	Power Switch Network Design for MTCMOS.	VLSI Design	2005	DBLP DOI BibTeX RDF
2	David Levacq, Vincent Dessard, Denis Flandre	Ultra-low power flip-flops for MTCMOS circuits.	ISCAS	2005	DBLP DOI BibTeX RDF
2	Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif	Approaches to run-time and standby mode leakage reduction in global buses.	ISLPED	2004	DBLP DOI BibTeX RDF	pulsed buses, leakage, repeaters, MTCMOS
2	Mircea R. Stan, Marco Barcella	MTCMOS with outer feedback (MTOF) flip-flops.	ISCAS	2003	DBLP DOI BibTeX RDF
2	Nikhil Jayakumar, Sunil P. Khatri	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.	ISLPED	2003	DBLP DOI BibTeX RDF	standby current, leakage current, standard cells, MTCMOS
2	Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, Shawki Areibi	Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique.	DAC	2002	DBLP DOI BibTeX RDF
2	Fatih Hamzaoglu, Mircea R. Stan	Circuit-level techniques to control gate leakage for sub-100nm CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, MTCMOS, gate leakage, domino circuits
2	Stephen V. Kosonocky, Michael Immediato, Peter E. Cottrell, Terence B. Hook, Randy W. Mann, Jeff Brown	Enchanced multi-threshold (MTCMOS) circuits using variable well bias.	ISLPED	2001	DBLP DOI BibTeX RDF	leakage control, low power digital circuit design, variable well bias, MTCMOS, multi-threshold
2	Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry	High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies.	ISLPED	2000	DBLP DOI BibTeX RDF
2	Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka	Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs.	ASP-DAC	1999	DBLP DOI BibTeX RDF
1	Hailong Jiao, Volkan Kursun	Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Yi-Ming Wang, Shi-Hao Chen, Mango Chia-Tso Chao	An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Hailong Jiao, Volkan Kursun	Noise-Aware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias.	Journal of Circuits, Systems, and Computers	2011	DBLP DOI BibTeX RDF
1	Hailong Jiao, Volkan Kursun	Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Henry X. F. Huang, Steven R. S. Shen, James B. Kuo	Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique.	PATMOS	2011	DBLP DOI BibTeX RDF
1	Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown	Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Hailong Jiao, Volkan Kursun	Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Hailong Jiao, Volkan Kursun	Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Hailong Jiao, Volkan Kursun	Smooth awakenings: Reactivation noise suppressed low-leakage and robust MTCMOS flip-flops.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Chih-Hsiang Lin, James B. Kuo	Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai	Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Qiang Zhou, Xin Zhao, Yici Cai, Xianlong Hong	An MTCMOS technology for low-power physical design.	Integration	2009	DBLP DOI BibTeX RDF
1	Chih-Hsiang Lin, James B. Kuo	Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique.	PATMOS	2009	DBLP DOI BibTeX RDF
1	Tsun-Ming Tseng, Mango Chia-Tso Chao, Chien Pang Lu, Chen Hsing Lo	Power-switch routing for coarse-grain MTCMOS technologies.	ICCAD	2009	DBLP BibTeX RDF
1	R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh	Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design.	ISQED	2009	DBLP DOI BibTeX RDF
1	Javid Jaffari, Mohab Anis	Thermal Driven Placement for Island-style MTCMOS FPGAs.	JCP	2008	DBLP DOI BibTeX RDF
1	Charbel J. Akl, Magdy A. Bayoumi	Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Ehsan Pakbaznia, Massoud Pedram	Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting.	DATE	2008	DBLP DOI BibTeX RDF
1	Andrea Calimera, Luca Benini, Enrico Macii	Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints.	DATE	2008	DBLP DOI BibTeX RDF
1	Christophe Giacomotto, Mandeep Singh, Milena Vratonjic, Vojin G. Oklobdzija	Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements.	PATMOS	2008	DBLP DOI BibTeX RDF	Clocked storage elements, VLSI, power consumption, flip-flops, voltage scaling, clock gating, power gating, energy optimization, MTCMOS, circuit optimization, circuit tuning, circuit analysis
1	David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat	Analysis and minimization of practical energy in 45nm subthreshold logic circuits.	ICCD	2008	DBLP DOI BibTeX RDF
1	Anand Ramalingam, Anirudh Devgan, David Z. Pan	Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce.	J. Low Power Electronics	2007	DBLP DOI BibTeX RDF
1	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Sachin Idgunji	Case study of a low power MTCMOS based ARM926 SoC : Design, analysis and test challenges.	ITC	2007	DBLP DOI BibTeX RDF
1	Aveek Sarkar, Shen Lin, Kai Wang	A methodology for analysis and verification of power gated circuits with correlated results.	ISLPED	2007	DBLP DOI BibTeX RDF	RedHawk, standby leakage current, design, verification, analysis, power gate, MTCMOS
1	Vishal Khandelwal, Ankur Srivastava	Monte-Carlo driven stochastic optimization framework for handling fabrication variability.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson	Overdrive Power-Gating Techniques for Total Power Minimization.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Vishal Khandelwal, Ankur Srivastava	Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Nikhil Jayakumar, Sunil P. Khatri	A Predictably Low-Leakage ASIC Design Style.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Naoaki Ohkubo, Kimiyoshi Usami	Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Enabling fine-grain leakage management by voltage anchor insertion.	DATE	2006	DBLP DOI BibTeX RDF
1	David Blaauw, Bo Zhai	Energy efficient design for subthreshold supply voltage operation.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Harmander Deogun, Dennis Sylvester, Kevin J. Nowka	Fine grained multi-threshold CMOS for enhanced leakage reduction.	ISCAS	2006	DBLP DOI BibTeX RDF
1	B. Chung, J. B. Kuo	Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Bong Hyun Lee, Young Hwan Kim, Kwang-Ok Jeong	Clock-Free MTCMOS Flip-Flops with High Speed and Low Power.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	An effective power mode transition technique in MTCMOS circuits.	DAC	2005	DBLP DOI BibTeX RDF
1	Hassan Hassan, Mohab Anis, Mohamed I. Elmasry	A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
1	David Blaauw, Anirudh Devgan, Farid N. Najm	Leakage power: trends, analysis and avoidance.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Hassan Hassan, Mohab Anis, Antoine El Daher, Mohamed I. Elmasry	Activity Packing in FPGAs for Leakage Power Reduction.	DATE	2005	DBLP DOI BibTeX RDF
1	Ranganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori	Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Chih-wen Hsueh, Tien-Fu Chen, Rong-Guey Chang, Shi-Wu Lo	Development of Architecture and Software Technologies in High-Performance Low-Power SoC Design.	RTCSA	2005	DBLP DOI BibTeX RDF	Tool Chain, Architecture, Compiler, System-on-Chip, Real-Time Operating System
1	Weiping Liao, Joseph M. Basile, Lei He	Microarchitecture-level leakage reduction with data retention.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner	The limit of dynamic voltage scaling and insomniac dynamic voltage scaling.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown	Analysis and Optimization of Enhanced MTCMOS Scheme.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Lawrence T. Clark, Rakesh Patel, Timothy S. Beatty	Managing standby and active mode leakage power in deep sub-micron design.	ISLPED	2004	DBLP DOI BibTeX RDF	SRAM leakage control, TGSRAM, battery lifetime, drowsy mode, thick gate shadow latch, transistor leakage, MTCMOS
1	Vishal Khandelwal, Ankur Srivastava	Leakage control through fine-grained placement and sizing of sleep transistors.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre	Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Mohab Anis, Shawki Areibi, Mohamed I. Elmasry	Design and optimization of multithreshold CMOS (MTCMOS) circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Frank Honoré, Benton H. Calhoun, Anantha Chandrakasan	Power-aware architectures and circuits for FPGA-based signal processing.	FPGA	2003	DBLP DOI BibTeX RDF
1	Chandramouli Gopalakrishnan, Srinivas Katkoori	KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths.	ICCD	2003	DBLP DOI BibTeX RDF
1	Chandramouli Gopalakrishnan, Srinivas Katkoori	Resource Allocation and Binding Approach for Low Leakage Power.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Mohab Anis, Mohamed W. Allam, Mohamed I. Elmasry	Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies.	IEEE Trans. VLSI Syst.	2002	DBLP DOI BibTeX RDF
1	Victor V. Zyuban, Stephen V. Kosonocky	Low power integrated scan-retention mechanism.	ISLPED	2002	DBLP DOI BibTeX RDF	balloon latch, data retention, low power, scan, leakage, latch, MTCMOS, subthreshold
1	James Kao, Siva Narendra, Anantha Chandrakasan	Subthreshold leakage modeling and reduction techniques.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Weiping Liao, Joseph M. Basile, Lei He	Leakage power modeling and reduction with data retention.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa	Automated selective multi-threshold design for ultra-low standby applications.	ISLPED	2002	DBLP DOI BibTeX RDF	standby leakage current, automated design, multi-threshold
1	James Kao, Siva Narendra, Anantha Chandrakasan	MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
1	Mircea R. Stan	Low threshold CMOS circuits with low standby current.	ISLPED	1998	DBLP DOI BibTeX RDF
1	James Kao, Anantha Chandrakasan, Dimitri Antoniadis	Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology.	DAC	1997	DBLP DOI BibTeX RDF