| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski |
A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.  |
J. Low Power Electronics  |
2011 |
DBLP BibTeX RDF |
|
| 1 | S. Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski |
Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang |
Temporal parallel simulation: A fast gate-level HDL simulation using higher level models. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dusung Kim, Maciej J. Ciesielski, Seiyang Yang |
A new distributed event-driven gate-level HDL simulation by accurate prediction. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Daniel Gomez-Prado, Dusung Kim, Maciej J. Ciesielski, Emmanuel Boutillon |
Retiming arithmetic datapaths using Timed Taylor Expansion Diagrams. |
HLDVT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski, Daniel Gomez-Prado, Q. Ren, Jérémie Guillot, Emmanuel Boutillon |
Optimization of Data-Flow Computations Using Canonical TED Representation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski, Jérémie Guillot, Daniel Gomez-Prado, Emmanuel Boutillon |
High-Level Dataflow Transformations Using Taylor Expansion Diagrams. |
IEEE Design & Test of Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, Jérémie Guillot, Emmanuel Boutillon |
Optimizing data flow graphs to minimize hardware implementation. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Kyuho Shim, Youngrae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang |
A fast two-pass HDL simulation with on-demand dump. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang |
Simulation Acceleration with HW Re-Compilation Avoidance. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon |
Data-flow transformations using Taylor expansion diagrams. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski, Priyank Kalla, Serkan Askar |
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
Register transfer level—design aids, arithmetic and logic structures—verification, symbolic and algebraic manipulation, verification |
| 1 | Jérémie Guillot, Emmanuel Boutillon, Q. Ren, Maciej J. Ciesielski, Daniel Gomez-Prado, Serkan Askar |
Efficient factorization of DSP transforms using taylor expansion diagrams. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhihong Zeng, Kesava R. Talupuru, Maciej J. Ciesielski |
Functional test generation based on word-level SAT. |
Journal of Systems Architecture |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhaojun Wo, Israel Koren, Maciej J. Ciesielski |
Yield-aware Floorplanning. |
DSD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhaojun Wo, Israel Koren, Maciej J. Ciesielski |
An ILP Formulation for Yield-driven Architectural Synthesis. |
DFT |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sungju Park, Sangwook Cho, Seiyang Yang, Maciej J. Ciesielski |
A new state assignment technique for testing and low power. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
low power, logic synthesis, fault coverage, scan design, state encoding |
| 1 | Görschwin Fey, Rolf Drechsler, Maciej J. Ciesielski |
Algorithms for Taylor Expansion Diagrams. |
ISMVL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maciej J. Ciesielski |
Fast Computation of Data Correlation Using BDDs. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Congguang Yang, Maciej J. Ciesielski |
BDS: a BDD-based logic optimization system. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyank Kalla, Maciej J. Ciesielski |
A comprehensive approach to the partial scan problem using implicitstate enumeration. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski, Serkan Askar, Samuel Levitin |
Analytical approach to layout generation of datapath cells. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre |
Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski |
Strategies for solving the Boolean satisfiability problem using binary decision diagrams. |
Journal of Systems Architecture |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre |
Functional Test Generation using Constraint Logic Programming. |
VLSI-SOC |
2001 |
DBLP BibTeX RDF |
|
| 1 | Zhihong Zeng, Priyank Kalla, Maciej J. Ciesielski |
LPSAT: a unified approach to RTL satisfiability. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Surendra Bommu, Niall O'Neill, Maciej J. Ciesielski |
Retiming-based factorization for sequential logic optimization. |
ACM Trans. Design Autom. Electr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
finite stat machines, retiming, sequential synthesis |
| 1 | Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal |
BDS: a BDD-based logic optimization system. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang |
A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Congguang Yang, Maciej J. Ciesielski |
Synthesis for Mixed CMOS/PTl Logic. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Durgam Vahia, Maciej J. Ciesielski |
Transistor level placement for full custom datapath cell design. |
ISPD |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyank Kalla, Maciej J. Ciesielski |
Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Serkan Askar, Maciej J. Ciesielski |
Analytical approach to custom datapath design. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Congguang Yang, Maciej J. Ciesielski, Vigyan Singhal |
BDD Decomposition for Efficient Logic Synthesis. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
Decomposition, Logic Synthesis, BDD, Dominators |
| 1 | Wayne P. Burleson, Maciej J. Ciesielski, Fabian Klass, W. Liu |
Wave-pipelining: a tutorial and research survey. |
IEEE Trans. VLSI Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyank Kalla, Maciej J. Ciesielski |
A comprehensive approach to the partial scan problem using implicit state enumeration. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Balakrishnan Iyer, Maciej J. Ciesielski |
Reencoding for cycle-time minimization under fixed encoding length. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyank Kalla, Maciej J. Ciesielski |
Testability of Sequential Circuits with Multi-Cycle False Path. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Imrich Chlamtac, Maciej J. Ciesielski, Andrea Fumagalli, Chester A. Ruszczyk, Gosse Wedzinga |
Intelligent Simulation for Computer Aided Design of Optical Networks. |
ONDM |
1997 |
DBLP BibTeX RDF |
|
| 1 | Balakrishnan Iyer, Maciej J. Ciesielski |
Metamorphosis: state assignment by retiming and re-encoding. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
Sequential Logic, Finite State Machine, Logic Synthesis, State Assignment, State Encoding |
| 1 | Wayne Burleson, L. W. Cotten, Fabian Klass, Maciej J. Ciesielski |
Forum: Wave-pipelining: Is it Practical? |
ISCAS |
1994 |
DBLP BibTeX RDF |
|
| 1 | Donald A. Joy, Maciej J. Ciesielski |
Clock period minimization with wave pipelining. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski, Seiyang Yang |
PLADE: a two-stage PLA decomposition. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Zafar Hasan, David Harrison, Maciej J. Ciesielski |
A Fast Partitioning Method for PLA-Based FPGAs. |
IEEE Design & Test of Computers |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Maya K. Yajnik, Maciej J. Ciesielski |
Finite State Machine Decomposition Using Multiway Partitioning. |
ICCD |
1992 |
DBLP BibTeX RDF |
|
| 1 | Seiyang Yang, Maciej J. Ciesielski |
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski, Jia-Jye Shen, Marc Davio |
A Unified Approach to Input-Output Encoding for FSM State Assignment. |
DAC |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Donald A. Joy, Maciej J. Ciesielski |
Placement for Clock Period Minimization With Multiple Wave Propagation. |
DAC |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski |
Layer assignment for VLSI interconnect delay minimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski, Edwin Kinnen |
Digraph Relaxation for 2-Dimensional Placement of IC Blocks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1987 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski |
Two-Dimensional Routing for the Silc Silicon Compiler. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1985 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski, Edwin Kinnen |
An analytical method for compacting routing area in integrated circuits. |
DAC |
1982 |
DBLP DOI BibTeX RDF |
|
| 1 | Maciej J. Ciesielski, Edwin Kinnen |
An optimum layer assignment for routing in ICs and PCBs. |
DAC |
1981 |
DBLP BibTeX RDF |
|
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