Search results for "Maged Ghoneima"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Maged Ghoneima, Yong Lian, Gabriele Manganaro, Shahriar Mirabbasi, Christian Piguet, Wouter A. Serdijn	Guest Editorial Special Issue on ISCAS 2010.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Sally Safwat, Ezz El-Din O. Hussein, Maged Ghoneima, Yehea I. Ismail	A 12Gbps all digital low power SerDes transceiver for on-chip networking.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Mina Raymond, Maged Ghoneima, Yehea I. Ismail	A dynamic calibration scheme for on-chip process and temperature variations.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De	Serial-Link Bus: A Low-Power On-Chip Bus Architecture.	IEEE Trans. on Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Muhammad M. Khellah, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De	Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek K. De	Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De	Formal derivation of optimal active shielding for low-power on-chip buses.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	Reducing the Data Switching Activity on Serial Link Buses.	ISQED	2006	DBLP DOI BibTeX RDF
1	Keith A. Bowman, James Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De	Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance.	ISLPED	2006	DBLP DOI BibTeX RDF	intra-die variations, multi-cycle interconnect, parameter fluctuations, time borrowing, interconnect, parameter variations, within-die variations, variation tolerant
1	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, Vivek De	Reducing the data switching activity of serialized datastreams.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail	Optimum positioning of interleaved repeaters in bidirectional buses.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Noha H. Mahmoud, Maged Ghoneima, Yehea I. Ismail	Physical limitations on the bit-rate of on-chip interconnects.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	damping factor, delay, interconnects, bit-rate
1	Maged Ghoneima, Yehea I. Ismail	Accurate decoupling of capacitively coupled buses.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Vivek De	Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De	Serial-link bus: a low-power on-chip bus architecture.	ICCAD	2005	DBLP BibTeX RDF
1	Muhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail	A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors.	ICCD	2005	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail	Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail	Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses.	ISLPED	2004	DBLP DOI BibTeX RDF	low power, interconnects, buses, coupling capacitance
1	Maged Ghoneima, Yehea I. Ismail	Effect of relative delay on the dissipated energy in coupled interconnects.	ISCAS	2004	DBLP BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail	Low power coupling-based encoding for on-chip buses.	ISCAS	2004	DBLP BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail	Formal derivation of optimal active shielding for low-power on-chip buses.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Maged Ghoneima, Yehea I. Ismail	Optimum positioning of interleaved repeaters In bidirectional buses.	DAC	2003	DBLP DOI BibTeX RDF	delay, interconnect, noise, repeaters, buses

Publications of "Maged Ghoneima" ( http://dblp.L3S.de/Authors/Maged_Ghoneima )