|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 1 occurrences of 1 keywords
|
|
|
|
|
Results
Found 7 publication records. Showing 7 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Shiyan Hu, Mahesh Ketkar, Jiang Hu |
Gate Sizing for Cell-Library-Based Designs.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahesh Ketkar, Eli Chiprout |
A microarchitecture-based framework for pre- and post-silicon power delivery analysis. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James Tschanz, Vivek De |
Comparative Analysis of Conventional and Statistical Design Techniques. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shiyan Hu, Mahesh Ketkar, Jiang Hu |
Gate Sizing For Cell Library-Based Designs. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahesh Ketkar, Sachin S. Sapatnekar |
Standby power optimization via transistor sizing and dual threshold voltage assignment. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar |
A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar |
Convex delay models for transistor sizing. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
SPICE |
Displaying result #1 - #7 of 7 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")