Search results for "Mahesh Mehendale"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Mahesh Mehendale, Subrangshu Das, Mohit Sharma, Mihir Mody, Ratna Reddy, Joseph Meehan, Hideo Tamama, Brian Carlson, Mike Polley	A true multistandard, programmable, low-power, full HD video-codec engine for smartphone SoC.	ISSCC	2012	DBLP DOI BibTeX RDF
1	Ajit Gupte, Bharadwaj Amrutur, Mahesh Mehendale, Ajit V. Rao, Madhukar Budagavi	Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding.	IEEE Trans. Circuits Syst. Video Techn.	2011	DBLP DOI BibTeX RDF
1	Nagendra Gulur, R. Manikantan, R. Govindarajan, Mahesh Mehendale	Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs.	PACT	2011	DBLP DOI BibTeX RDF
1	Subash G. Chandar, Mahesh Mehendale, R. Govindarajan	Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding.	VLSI Signal Processing	2006	DBLP DOI BibTeX RDF	embedded DSP systems, re-configurable architecture, code compression, energy reduction
1	Mahesh Mehendale	SoC - The Road Ahead.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Mahesh Mehendale	Challenges in the Design of Embedded Real-time DSP SoCs.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Amitabh Menon, S. K. Nandy, Mahesh Mehendale	Multivoltage scheduling with voltage-partitioned variable storage.	ISLPED	2003	DBLP DOI BibTeX RDF	multivoltage, high level synthesis, datapath synthesis
1	Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei	Emerging markets: design goes global.	DAC	2003	DBLP DOI BibTeX RDF
1	Vikas Agrawal, Anand Pande, Mahesh Mehendale	High Level Synthesis Of Multi-Precision Data Flow Graphs.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, Santhosh Kumar Amanna	Functional Verification of Programmable DSP Cores.	VLSI Design	2001	DBLP BibTeX RDF
1	Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair	Performance Considerations in Embedded DSP based System-On-a-Chip Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Subash G. Chandar, Mahesh Mehendale, R. Govindarajan	Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding.	ICCAD	2001	DBLP BibTeX RDF
1	Mahesh Mehendale, Sunil D. Sherlekar	Power Reduction Techniques for Portable DSP Applications.	VLSI Design	2000	DBLP BibTeX RDF
1	M. N. Mahesh, Mahesh Mehendale	Low Power Realization of Residue Number System Based FIR Filters.	VLSI Design	2000	DBLP DOI BibTeX RDF	Low power implementation, DSP, Residue Number System(RNS), FIR filters
1	M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale	Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms.	VLSI Design	1999	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, Sunil D. Sherlekar	Low Power Code Generation of Multiplication-free Linear Transforms.	VLSI Design	1999	DBLP BibTeX RDF
1	M. N. Mahesh, Mahesh Mehendale	Improving performance of high precision signal processing algorithms on programmable DSPs.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Low-power realization of FIR filters on programmable DSPs.	IEEE Trans. VLSI Syst.	1998	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar	Low Power Realization of FIR Filters Implemented using Distributed Arithmetic.	ASP-DAC	1998	DBLP BibTeX RDF
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters.	VLSI Design	1998	DBLP DOI BibTeX RDF	Hardware/Software High Level Synthesis, Low Power Design, FIR Filters
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Extensions to Programmable DSP architectures for Reduced Power Dissipation.	VLSI Design	1998	DBLP DOI BibTeX RDF	Low Power Design, DSP Architecture
1	Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh	Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters.	VLSI Design	1998	DBLP DOI BibTeX RDF	High Level Synthesis-Transformations, FIR Filters
1	Amit Sinha, Mahesh Mehendale	mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic.	VLSI Design	1998	DBLP DOI BibTeX RDF	FIR Filters, Distributed Arithmetic, Area Estimation
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters.	VLSI Design	1997	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar	Optimized Code Generation of Multiplication-free Linear Transforms.	DAC	1996	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Low power realization of FIR filters using multirate architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF	low power realization, multirate architectures, computationally efficient implementations, power dissipation reduction, dedicated ASIC implementation, TMS320C2x/C5x programmable DSP, computational complexity, computational complexity, application specific integrated circuits, power analysis, digital filters, FIR filters, FIR filters, digital signal processing chips
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Techniques for low power realization for FIR filters.	ASP-DAC	1995	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, M. K. Ram Prasad	AATMA: an algorithm for technology mapping for antifuse-based FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	AATMA, antifuse-based FPGAs, logic module structure, complex functions, signature-matching based approach, mapping quality, logic module architectures, field programmable gate arrays, directed graphs, combinational circuits, logic CAD, technology mapping, execution times
1	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh	Synthesis of multiplier-less FIR filters with minimum number of additions.	ICCAD	1995	DBLP DOI BibTeX RDF	MCM based structures, iterative elimination, low pass FIR filters, circuit CAD, FIR filters, network synthesis, optimizing transformations, binary representations
1	Mahesh Mehendale	Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures.	VLSI Design	1994	DBLP BibTeX RDF
1	Mahesh Mehendale, Biswadip Mitra	An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis.	VLSI Design	1994	DBLP BibTeX RDF
1	Mahesh Mehendale	MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs.	DAC	1993	DBLP DOI BibTeX RDF
1	Mahesh Mehendale, Kaushik Roy	Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures.	VLSI Design	1993	DBLP BibTeX RDF
1	Mahesh Mehendale, P. Murugavel, M. Poornima	SLIM: A System for ASIC Library Management.	ICCAD	1991	DBLP BibTeX RDF

Publications of "Mahesh Mehendale" ( http://dblp.L3S.de/Authors/Mahesh_Mehendale )