Search results for "Maksim Jenihhin"

Found 15 publication records. Showing 15 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov	Automated test bench generation for high-level synthesis flow ABELITE.	EWDTS	2011	DBLP DOI BibTeX RDF
1	Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara	Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits.	European Test Symposium	2011	DBLP DOI BibTeX RDF
1	Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova	An approach for PSL assertion coverage analysis with high-level decision diagrams.	EWDTS	2010	DBLP DOI BibTeX RDF
1	Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko	Constraint-based test pattern generation at the Register-Transfer Level.	DDECS	2010	DBLP DOI BibTeX RDF
1	Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar	PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams.	J. Electronic Testing	2009	DBLP BibTeX RDF
1	Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin	Mixed hierarchical-functional fault models for targeting sequential cores.	Journal of Systems Architecture - Embedded Systems Design	2008	DBLP DOI BibTeX RDF
1	Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee	Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance.	DELTA	2008	DBLP DOI BibTeX RDF	high-level decision diagrams, fault tolerance, fault simulation
1	Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz	Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC.	DSD	2008	DBLP DOI BibTeX RDF
1	Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar	Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation.	European Test Symposium	2008	DBLP DOI BibTeX RDF	assertion checking, decision diagrams, Property Specification Language
1	Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee	Code Coverage Analysis using High-Level Decision Diagrams.	DDECS	2008	DBLP DOI BibTeX RDF
1	Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski	Layout to Logic Defect Analysis for Hierarchical Test Generation.	DDECS	2007	DBLP BibTeX RDF
1	Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin	Test Time Minimization for Hybrid BIST of Core-Based Systems.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	hybrid BIST, SoC, self-test
1	Raimund Ubar, Maksim Jenihhin	Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting.	DELTA	2004	DBLP DOI BibTeX RDF
1	Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin	Test Time Minimization for Hybrid BIST of Core-Based Systems.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin	Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture.	DFT	2003	DBLP DOI BibTeX RDF

Publications of "Maksim Jenihhin" ( http://dblp.L3S.de/Authors/Maksim_Jenihhin )