Search results for "Malay K. Ganai"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Chao Wang, Sudipta Kundu, Rhishikesh Limaye, Malay K. Ganai, Aarti Gupta	Symbolic predictive analysis for concurrent programs.	Formal Asp. Comput.	2011	DBLP DOI BibTeX RDF
1	Chao Wang, Malay K. Ganai	Predicting Concurrency Failures in the Generalized Execution Traces of x86 Executables.	RV	2011	DBLP DOI BibTeX RDF
1	Malay K. Ganai	Scalable and precise symbolic analysis for atomicity violations.	ASE	2011	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Nipun Arora, Chao Wang, Aarti Gupta, Gogul Balakrishnan	BEST: A symbolic testing tool for predicting multi-threaded program failures.	ASE	2011	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Chao Wang	Interval Analysis for Concurrent Trace Programs Using Transaction Sequence Graphs.	RV	2010	DBLP DOI BibTeX RDF
1	Franjo Ivancic, Malay K. Ganai, Sriram Sankaranarayanan, Aarti Gupta	Numerical stability analysis of floating-point computations using software model checking.	MEMOCODE	2010	DBLP DOI BibTeX RDF
1	Chao Wang, Rhishikesh Limaye, Malay K. Ganai, Aarti Gupta	Trace-Based Symbolic Analysis for Atomicity Violations.	TACAS	2010	DBLP DOI BibTeX RDF
1	Malay K. Ganai	Propelling SAT and SAT-based BMC using careset.	FMCAD	2010	DBLP BibTeX RDF
1	Gogul Balakrishnan, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Vineet Kahlon, Weihong Li, Naoto Maeda, Nadia Papakonstantinou, Sriram Sankaranarayanan, Nishant Sinha, Chao Wang	Scalable and precise program analysis at NEC.	FMCAD	2010	DBLP BibTeX RDF
1	Sicun Gao, Malay K. Ganai, Franjo Ivancic, Aarti Gupta, Sriram Sankaranarayanan, Edmund M. Clarke	Integrating ICP and LRA solvers for deciding nonlinear real arithmetic problems.	FMCAD	2010	DBLP BibTeX RDF
1	Sudipta Kundu, Malay K. Ganai, Chao Wang	Contessa: Concurrency Testing Augmented with Symbolic Analysis.	CAV	2010	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Chao Wang, Weihong Li	Efficient state space exploration: Interleaving stateless and state-based model checking.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Weihong Li	Bang for the buck: Improvising and scheduling verification engines for effective resource utilization.	MEMOCODE	2009	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Franjo Ivancic	Efficient decision procedure for non-linear arithmetic constraints using CORDIC.	FMCAD	2009	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Sudipta Kundu	Reduction of Verification Conditions for Concurrent System Using Mutually Atomic Transactions.	SPIN	2009	DBLP DOI BibTeX RDF
1	Chao Wang, Sudipta Kundu, Malay K. Ganai, Aarti Gupta	Symbolic Predictive Analysis for Concurrent Programs.	FM	2009	DBLP DOI BibTeX RDF
1	Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Pranav Ashar	Efficient SAT-based bounded model checking for software verification.	Theor. Comput. Sci.	2008	DBLP DOI BibTeX RDF
1	Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar	Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Gogul Balakrishnan, Malay K. Ganai	PED: Proof-Guided Error Diagnosis by Triangulation of Program Error Causes.	SEFM	2008	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta	Tunneling and slicing: towards scalable BMC.	DAC	2008	DBLP DOI BibTeX RDF	CFG, partitioning, slice, SMT, tunnel, EFSM, CSR, BMC
1	Sudipta Kundu, Malay K. Ganai, Rajesh Gupta	Partial order reduction for scalable testing of systemC TLM designs.	DAC	2008	DBLP DOI BibTeX RDF	simulation, verification, testing, partial-order reduction
1	Malay K. Ganai, Aarti Gupta	Efficient Modeling of Concurrent Systems in BMC.	SPIN	2008	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta	Completeness in SMT-based BMC for Software Programs.	DATE	2008	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Weihong Li	d-TSR: Parallelizing SMT-Based BMC Using Tunnels over a Distributed Framework.	Haifa Verification Conference	2008	DBLP DOI BibTeX RDF
1	Malay K. Ganai	Efficient Decision Procedure for Bounded Integer Non-linear Operations Using SMT().	Haifa Verification Conference	2008	DBLP DOI BibTeX RDF
1	Chao Wang, Malay K. Ganai, Shuvendu K. Lahiri, Daniel Kroening	Embedded software verification: challenges and solutions.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Muralidhar Talupur, Aarti Gupta	SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in Solving Difference Logic.	JSAT	2007	DBLP BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Verification of Embedded Memory Systems using Efficient Memory Modeling	CoRR	2007	DBLP BibTeX RDF
1	Malay K. Ganai, Aarti Gupta	Efficient BMC for Multi-Clock Systems with Clocked Specifications.	ASP-DAC	2007	DBLP DOI BibTeX RDF	OpenCores multiclock system benchmarks, clocked specifications, multiphased clocks, level-sensitive latches, SAT-based bounded model checking, synchronous multiclock systems, clocked LTL properties, clock modeling schemes, clock constraints, loop-checks, gated clocks
1	Malay K. Ganai, Akira Mukaiyama, Aarti Gupta, Kazutoshi Wakabayashi	Synthesizing "Verification Aware" Models: Why and How?	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar	Efficient distributed SAT and SAT-based distributed Bounded Model Checking.	STTT	2006	DBLP DOI BibTeX RDF	Distributed-SAT, Parallel SAT, Model Checking, Formal Verification, SAT, BMC
1	Malay K. Ganai, Muralidhar Talupur, Aarti Gupta	SDSAT: Tight Integration of Small Domain Encoding and Lazy Approaches in a Separation Logic Solver.	TACAS	2006	DBLP DOI BibTeX RDF
1	Chao Wang, Aarti Gupta, Malay K. Ganai	Predicate learning and selective theory deduction for a difference logic solver.	DAC	2006	DBLP DOI BibTeX RDF	difference logic, SAT, decision procedure, SMT solver
1	Aarti Gupta, Malay K. Ganai, Chao Wang	SAT-Based Verification Methods and Applications in Hardware Verification.	SFM	2006	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta	Accelerating high-level bounded model checking.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems.	TACAS	2005	DBLP DOI BibTeX RDF
1	Himanshu Jain, Franjo Ivancic, Aarti Gupta, Malay K. Ganai	Localization and Register Sharing for Predicate Abstraction.	TACAS	2005	DBLP DOI BibTeX RDF
1	Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti Gupta	Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination.	LPAR	2005	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Beyond safety: customized SAT-based model checking.	DAC	2005	DBLP DOI BibTeX RDF	circuit cofactoring, unbounded model checking, formal verification, SAT, liveness, bounded model checking, LTL
1	Aarti Gupta, Malay K. Ganai, Pranav Ashar	Lazy Constraints and SAT Heuristics for Proof-Based Abstraction.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Verification of Embedded Memory Systems using Efficient Memory Modeling.	DATE	2005	DBLP DOI BibTeX RDF
1	Franjo Ivancic, Zijiang Yang, Malay K. Ganai, Aarti Gupta, Ilya Shlyakhter, Pranav Ashar	F-Soft: Software Verification Platform.	CAV	2005	DBLP DOI BibTeX RDF
1	Franjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay K. Ganai	Model Checking C Programs Using F-SOFT.	ICCD	2005	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Efficient Modeling of Embedded Memories in Bounded Model Checking.	CAV	2004	DBLP DOI BibTeX RDF
1	Pranav Ashar, Malay K. Ganai, Aarti Gupta, Franjo Ivancic, Zijiang Yang	Efficient SAT-based Bounded Model Checking for Software Verification.	ISoLA (Preliminary proceedings)	2004	DBLP BibTeX RDF
1	Malay K. Ganai, Aarti Gupta, Pranav Ashar	Efficient SAT-based unbounded symbolic model checking using circuit cofactoring.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar	Learning from BDDs in SAT-based bounded model checking.	DAC	2003	DBLP DOI BibTeX RDF	BDD learning, learning, SAT, BDDs, bounded model checking, boolean satisfiability, SAT solvers, property checking
1	Malay K. Ganai, Aarti Gupta, Zijiang Yang, Pranav Ashar	Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking.	CHARME	2003	DBLP DOI BibTeX RDF
1	Aarti Gupta, Malay K. Ganai, Chao Wang, Zijiang Yang, Pranav Ashar	Abstraction and BDDs Complement SAT-Based BMC in DiVer.	CAV	2003	DBLP DOI BibTeX RDF
1	Aarti Gupta, Malay K. Ganai, Zijiang Yang, Pranav Ashar	Iterative Abstraction using SAT-based BMC with Proof Analysis.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai	Robust Boolean reasoning for equivalence checking and functional property verification.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao Zhang, Sharad Malik	Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver.	DAC	2002	DBLP DOI BibTeX RDF	boolean constraint propagation (BCP), bounded model checking (BMC), conjunctive normal form (CNF), boolean satisfiability (SAT)
1	Malay K. Ganai, Adnan Aziz	Improved SAT-Based Bounded Reachability Analysis.	VLSI Design	2002	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Praveen Yalagandula, Adnan Aziz, Andreas Kuehlmann, Vigyan Singhal	SIVA: A System for Coverage-Directed State Space Search.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	formal methods, coverage, functional verification, guided search
1	Malay K. Ganai, Adnan Aziz	Rarity based guided state space search.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF	simulation, formal methods, coverage, BDDs, functional verification
1	Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi	Circuit-based Boolean Reasoning.	DAC	2001	DBLP DOI BibTeX RDF
1	Malay K. Ganai, Adnan Aziz, Andreas Kuehlmann	Enhancing Simulation with BDDs and ATPG.	DAC	1999	DBLP DOI BibTeX RDF	simulation, formal verification, coverage, ATPG, BDDs
1	Tai-Hung Liu, Malay K. Ganai, Adnan Aziz, Jeffrey L. Burns	Performance Driven Synthesis for Pass-Transistor Logic.	VLSI Design	1999	DBLP BibTeX RDF

Publications of "Malay K. Ganai" ( http://dblp.L3S.de/Authors/Malay_K._Ganai )