Search results for "Manfred Glesner"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	Wormhole cut-through switching: Flit-level messages interleaving for virtual-channelless network-on-chip.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networks-on-Chip.	IEEE Trans. Parallel Distrib. Syst.	2011	DBLP DOI BibTeX RDF	tree-based and multipath-based multicast routing, Id-tag-based wormhole packet switching, runtime adaptive routing and scheduling, Network-on-chip
1	Surapong Pongyupinpanich, Manfred Glesner	Pipelined Floating-Point Architecture for a Phase and Magnitude Detector Based on CORDIC.	FPL	2011	DBLP DOI BibTeX RDF
1	François Philipp, Manfred Glesner	Mechanisms and Architecture for the Dynamic Reconfiguration of an Advanced Wireless Sensor Node.	FPL	2011	DBLP DOI BibTeX RDF	Wireless Sensor Networks, Dynamic Reconfiguration, Coarse-Grained Reconfigurable Architecture
1	François Philipp, Faizal Arya Samman, Manfred Glesner	Design of an autonomous platform for distributed sensing-actuating systems.	International Symposium on Rapid System Prototyping	2011	DBLP DOI BibTeX RDF
1	Surapong Pongyupinpanich, Manfred Glesner	On-chip efficient Round-Robin scheduler for high-speed interconnection.	International Symposium on Rapid System Prototyping	2011	DBLP DOI BibTeX RDF
1	François Philipp, Manfred Glesner	A Multi-level Reconfigurable Architecture for a Wireless Sensor Node Coprocessing Unit.	IPDPS Workshops	2011	DBLP DOI BibTeX RDF
1	Ping Zhao, Manfred Glesner	RF energy harvester design with autonomously adaptive impedance matching network based on auxiliary charge-pump rectifier.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Faizal Arya Samman, Surapong Pongyupinpanich, Manfred Glesner	Reconfigurable streaming processor core with interconnected floating-point arithmetic units for multicore adaptive signal processing systems.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Thomas Hollstein, Faizal Arya Samman, Ashok Jaiswal, Haoyuan Ying, Manfred Glesner, Klaus Hofmann	Invited paper: Design criteria for dependable System-on-Chip architectures.	ReCoSoC	2011	DBLP DOI BibTeX RDF
1	Sanna Määttä, Leandro Möller, Leandro Soares Indrusiak, Luciano Ost, Manfred Glesner, Jari Nurmi, Fernando Moraes	Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms.	IJERTCS	2010	DBLP DOI BibTeX RDF
1	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	Adaptive and Deadlock-Free Tree-Based Multicast Routing for Networks-on-Chip.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Heiko Hinkelmann, Peter Zipf, Manfred Glesner	Dynamically Reconfigurable Systems for Wireless Sensor Networks.	Dynamically Reconfigurable Systems	2010	DBLP DOI BibTeX RDF
1	Leandro Möller, Peter Fischer, Fernando Moraes, Leandro Soares Indrusiak, Manfred Glesner	Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers.	FPL	2010	DBLP DOI BibTeX RDF
1	Heiko Hinkelmann, Peter Zipf, Jia Li, Guifang Liu, Manfred Glesner	On the design of reconfigurable multipliers for integer and Galois field multiplication.	Microprocessors and Microsystems - Embedded Hardware Design	2009	DBLP DOI BibTeX RDF
1	Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner	Low-Power Coding for Networks-on-Chip with Virtual Channels.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Peter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, Manfred Glesner	A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips.	Int. J. Reconfig. Comp.	2009	DBLP DOI BibTeX RDF
1	Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, Manfred Glesner	Providing Memory Management Abstraction for Self-Reconfigurable Video Processing Platforms.	Int. J. Reconfig. Comp.	2009	DBLP DOI BibTeX RDF
1	Heiko Hinkelmann, Peter Zipf, Manfred Glesner	Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes.	FPL	2009	DBLP DOI BibTeX RDF
1	Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner	An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs.	FPL	2009	DBLP DOI BibTeX RDF
1	Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf	Towards a unique FPGA-based identification circuit using process variations.	FPL	2009	DBLP DOI BibTeX RDF
1	Petru Bogdan Bacinschi, Manfred Glesner	A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures.	VLSI-SoC	2009	DBLP DOI BibTeX RDF
1	T. Chun Pong Chau, S. Man Ho Ho, Philip Heng Wai Leong, Peter Zipf, Manfred Glesner	Generation of Synthetic Floating-Point benchmark circuits.	IPDPS	2009	DBLP DOI BibTeX RDF
1	Andre Guntoro, Manfred Glesner	A flexible floating-point wavelet transform and wavelet packet processor.	DATE	2009	DBLP BibTeX RDF
1	Radu Dogaru, Manfred Glesner	A fast and compact classifier based on sorting in an iteratively expanded input space.	Int. J. Intell. Syst.	2008	DBLP DOI BibTeX RDF
1	Manfred Glesner, Tudor Murgan, Thomas Hollstein	Hardware Based Rapid Prototyping.	Wiley Encyclopedia of Computer Science and Engineering	2008	DBLP DOI BibTeX RDF
1	Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner	Coarse-grained reconfiguration.	FPL	2008	DBLP DOI BibTeX RDF
1	Andre Guntoro, Manfred Glesner	A lifting-based DWT and IDWT processor with multi-context configuration and normalization factor.	FPL	2008	DBLP DOI BibTeX RDF
1	Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Matthias Alles, Timo Vogt, Norbert Wehn, Götz Kappen, Tobias G. Noll	Application-specific reconfigurable processors.	FPL	2008	DBLP DOI BibTeX RDF
1	Andre Guntoro, Manfred Glesner	High-performance fpga-based floating-point adder with three inputs.	FPL	2008	DBLP DOI BibTeX RDF
1	Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Fernando Moraes, Manfred Glesner	Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Heiko Hinkelmann, Andreas Reinhardt, Manfred Glesner	A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
1	Christopher Spies, Peter Zipf, Manfred Glesner, Harald Klingbeil	Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II.	IEEE International Workshop on Rapid System Prototyping	2008	DBLP DOI BibTeX RDF
1	Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner	PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Enkhbold Ochirsuren, Leandro Soares Indrusiak, Manfred Glesner	An Actor-Oriented Group Mobility Model for Wireless Ad Hoc Sensor Networks.	ICDCS Workshops	2008	DBLP DOI BibTeX RDF
1	Luciano Ost, Fernando Gehm Moraes, Leandro Möller, Leandro Soares Indrusiak, Manfred Glesner, Sanna Määttä, Jari Nurmi	A simplified executable model to evaluate latency and throughput of networks-on-chip.	SBCCI	2008	DBLP DOI BibTeX RDF	performance evaluation, modeling, networks-on-chip
1	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	Flexible parallel pipeline network-on-chip based on dynamic packet identity management.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Andre Guntoro, Hans-Peter Keil, Manfred Glesner	Configurable VLSI Architecture of a General Purpose Lifting-based Wavelet Processor.	SIGMAP	2008	DBLP BibTeX RDF
1	Andre Guntoro, Manfred Glesner	Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters.	ASAP	2008	DBLP DOI BibTeX RDF
1	Kurt Franz Ackermann, Burghard Hoffmann, Leandro Soares Indrusiak, Manfred Glesner	Enabling self-reconfiguration on a video processing platform.	SIES	2008	DBLP DOI BibTeX RDF
1	Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Möller, Jari Nurmi, Manfred Glesner, Fernando Moraes	Validation of executable application models mapped onto network-on-chip platforms.	SIES	2008	DBLP DOI BibTeX RDF
1	Enkhbold Ochirsuren, Heiko Hinkelmann, Leandro Soares Indrusiak, Manfred Glesner	TinyOS Extensions for a Wireless Sensor Network Node Based on a Dynamically Reconfigurable Processor.	DIPES	2008	DBLP DOI BibTeX RDF
1	Massoud Momeni, Petru Bogdan Bacinschi, Manfred Glesner	Comparison of Opamp-Based and Comparator-Based Delta-Sigma Modulation.	DATE	2008	DBLP DOI BibTeX RDF
1	Faizal Arya Samman, Thomas Hollstein, Manfred Glesner	Multicast Parallel Pipeline Router Architecture for Network-on-Chip.	DATE	2008	DBLP DOI BibTeX RDF
1	Petru Bogdan Bacinschi, Tudor Murgan, Klaus Koch, Manfred Glesner	An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs.	DATE	2008	DBLP DOI BibTeX RDF
1	Sujan Pandey, Rolf Drechsler, Tudor Murgan, Manfred Glesner	Process variations aware robust on-chip bus architecture synthesis for MPSoCs.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Alberto García Ortiz, Tudor Murgan, Manfred Glesner	Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear Systems.	J. Low Power Electronics	2007	DBLP DOI BibTeX RDF
1	Sujan Pandey, Manfred Glesner	Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Thomas Hollstein, Manfred Glesner	Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms.	Computers & Electrical Engineering	2007	DBLP DOI BibTeX RDF
1	Heiko Hinkelmann, Peter Zipf, Manfred Glesner, Thilo Pionteck	Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme).	it - Information Technology	2007	DBLP DOI BibTeX RDF
1	Peter Zipf, Heiko Hinkelmann, Lei Deng, Manfred Glesner, Holger Blume, Tobias G. Noll	A Power Estimation Model for an FPGA-based Softcore Processor.	FPL	2007	DBLP DOI BibTeX RDF
1	José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis	Inserting Data Encoding Techniques into NoC-Based Systems.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner	On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Leandro Soares Indrusiak, Manfred Glesner	Specification of alternative execution semantics of UML sequence diagrams within actor-oriented models.	SBCCI	2007	DBLP DOI BibTeX RDF	actor-orientation, UML, embedded systems, sequence diagram, message sequence charts, electronic system level
1	Mihail Petrov, Manfred Glesner	A Scalable Resampling Architecture.	GLOBECOM	2007	DBLP DOI BibTeX RDF
1	Mihail Petrov, Manfred Glesner	An Efficient Fractional-Rate Interpolation Architecture.	GLOBECOM	2007	DBLP DOI BibTeX RDF
1	Leandro Soares Indrusiak, Andreas Thuy, Manfred Glesner	Interactive presentation: Executable system-level specification models containing UML-based behavioral patterns.	DATE	2007	DBLP DOI BibTeX RDF
1	Gilles Sassatelli, Manfred Glesner, Christophe Bobda, Pascal Benoit (eds.)	Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2007, Montpellier, France, June 2007	ReCoSoC	2007	DBLP BibTeX RDF
1	Tudor Murgan, Andre Guntoro, Heiko Hinkelmann, Petru Bogdan Bacinschi, Manfred Glesner	Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling.	ReCoSoC	2007	DBLP BibTeX RDF
1	Kurt Franz Ackermann, Leandro Soares Indrusiak, Manfred Glesner	System Level Design of a Dynamically Self-Reconfigurable Image Processing System.	ReCoSoC	2007	DBLP BibTeX RDF
1	Peter Zipf, Heiko Hinkelmann, Felix Missel, Manfred Glesner	A Customizable LEON2-Based VLIW Processor.	ReCoSoC	2007	DBLP BibTeX RDF
1	Heiko Hinkelmann, Tudor Murgan, Guifang Liu, Peter Zipf, Manfred Glesner	On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication.	ReCoSoC	2007	DBLP BibTeX RDF
1	Heiko Hinkelmann, Andreas Gunberg, Peter Zipf, Leandro Soares Indrusiak, Manfred Glesner	Multitasking Support for Dynamically Reconfig Urable Systems.	FPL	2006	DBLP DOI BibTeX RDF
1	Sujan Pandey, Manfred Glesner	Energy Efficient Statistical On-Chip Communication Bus Synthesis for a Reconfigurable Architecture.	FPL	2006	DBLP DOI BibTeX RDF
1	Heiko Hinkelmann, Peter Zipf, Manfred Glesner	Design Concepts for a Dynamically ReconfigurableWireless Sensor Node.	AHS	2006	DBLP DOI BibTeX RDF
1	Romualdo Begale Prudencio, Leandro Soares Indrusiak, Manfred Glesner	An Efficient Hardware Implementation of a Self-Adaptable Equalizer for WCDMA Downlink UMTS Standard.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes	Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Clemens Schlachta, Manfred Glesner	A CMOS Compatible Charge Recovery Logic Family for Low Supply Voltages.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Tudor Murgan, Petru Bogdan Bacinschi, Alberto García Ortiz, Manfred Glesner	Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance.	PATMOS	2006	DBLP DOI BibTeX RDF
1	José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis	Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Heiko Hinkelmann, Peter Zipf, Manfred Glesner	A metric for the energy-efficiency of dynamically reconfigurable systems.	ARCS Workshops	2006	DBLP BibTeX RDF
1	Sujan Pandey, Nurten Utlu, Manfred Glesner	Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Sujan Pandey, Tudor Murgan, Manfred Glesner	Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner	Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Leandro Soares Indrusiak, Manfred Glesner	An Actor-Oriented Model-Based Design Flow for Systems-on-Chip.	MBEES	2006	DBLP BibTeX RDF
1	Peter Zipf, Manfred Glesner	Towards an Automated Design of Application-specific Reconfigurable Logic.	Dynamically Reconfigurable Architectures	2006	DBLP BibTeX RDF
1	Sujan Pandey, Manfred Glesner	Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint.	DAC	2006	DBLP DOI BibTeX RDF	communication bus synthesis, voltage scaling
1	Andreas Thuy, Leandro Soares Indrusiak, Manfred Glesner	Applying Communication Patterns to Actor-Oriented Models.	FDL	2006	DBLP BibTeX RDF
1	Oliver Soffke, Peter Zipf, Tudor Murgan, Manfred Glesner	A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits.	DATE	2006	DBLP DOI BibTeX RDF
1	Sujan Pandey, Manfred Glesner	Energy efficient MPSoC on-chip communication bus synthesis using voltage scaling technique.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner	Implementation of Realtime and Highspeed Phase Detector on FPGA.	ARC	2006	DBLP DOI BibTeX RDF
1	Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner	A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier	Reduction of Crosstalk Pessimism using Tendency Graph Approach.	ICCD	2006	DBLP BibTeX RDF
1	Kurt Franz Ackermann, Friedhelm Mayer, Leandro Soares Indrusiak, Manfred Glesner	Adaptable Image Processing System based on FPGA Modular Multi Kernel Instantiations.	ReCoSoC	2006	DBLP BibTeX RDF
1	Hua Zhong, Leandro Soares Indrusiak, Heiko Hinkelmann, Manfred Glesner	Exploring Functional Unit Parallelism in Reconfigurable Computing Platforms.	ReCoSoC	2006	DBLP BibTeX RDF
1	Heiko Hinkelmann, Peter Zipf, Manfred Glesner	A Concept for a Profile-based Dynamic Reconfiguration Mechanism.	ReCoSoC	2006	DBLP BibTeX RDF
1	Gilles Sassatelli, Leandro Soares Indrusiak, Manfred Glesner, Lionel Torres (eds.)	Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2006, Montpellier, France, July 2006	ReCoSoC	2006	DBLP BibTeX RDF
1	Cristian Chitu, Manfred Glesner	An FPGA implementation of the AES-Rijndael in OCB/ECB modes of operation.	Microelectronics Journal	2005	DBLP DOI BibTeX RDF
1	Manfred Glesner, Heiko Hinkelmann, Thomas Hollstein, Leandro Soares Indrusiak, Tudor Murgan, Abdulfattah Mohammad Obeid, Mihail Petrov, Thilo Pionteck, Peter Zipf	Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques.	SAMOS	2005	DBLP DOI BibTeX RDF
1	Diego Fernando Jimenez Orostegui, Leandro Soares Indrusiak, Manfred Glesner	Proxy-Based Integration of Reconfigurable Hardware Within Simulation Environments: Improving E-Learning Experience in Microelectronics.	MSE	2005	DBLP DOI BibTeX RDF
1	Peter Zipf, Oliver Soffke, Andre Schumacher, Clemens Schlachta, Radu Dogaru, Manfred Glesner	A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata.	FPL	2005	DBLP BibTeX RDF
1	Peter Zipf, Oliver Soffke, Andre Schumacher, Radu Dogaru, Manfred Glesner	Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata.	FPL	2005	DBLP BibTeX RDF
1	Sujan Pandey, Manfred Glesner, Max Mühlhäuser	On-Chip Communication Topology Synthesis for a Shared Memory Architecture.	FPL	2005	DBLP BibTeX RDF
1	Leandro Soares Indrusiak, Romualdo Begale Prudencio, Manfred Glesner	Modeling and Prototyping of Communication Systems Using Java: A Case Study.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
1	Heiko Hinkelmann, Thilo Pionteck, Oliver Kleine, Manfred Glesner	Prozessorintegration und Speicheranbindung dynamisch rekonfigurierbarer Funktionseinheiten.	ARCS Workshops	2005	DBLP BibTeX RDF
1	Sujan Pandey, Manfred Glesner, Max Mühlhäuser	Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture.	SBCCI	2005	DBLP DOI BibTeX RDF	on-chip communication architecture synthesis, optimization, algorithms
1	Elvio Dutra, Leandro Soares Indrusiak, Manfred Glesner	Non-linear addressing scheme for a lookup-based transformation function in a reconfigurable noise generator.	SBCCI	2005	DBLP DOI BibTeX RDF	addressing scheme, gauss, noise generator, noise, lookup-table, normal distribution, white noise, LUT, transformation function, probability distribution function
1	Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner	On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	Mihail Petrov, Manfred Glesner	Optimal FFT Architecture Selection for OFDM Receivers on FPGA.	FPT	2005	DBLP BibTeX RDF

Publications of "Manfred Glesner" ( http://dblp.L3S.de/Authors/Manfred_Glesner )