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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2 occurrences of 2 keywords
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Results
Found 22 publication records. Showing 22 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Manthena Vamshi Krishna, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo |
A Low-Power Single-Phase Clock Multiband Flexible Divider.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Ali Meaamar, Chirn Chye Boon, Xiaomeng Shi, Wei Meng Lim, Kiat Seng Yeo, Manh Anh Do |
A 3.1-8 GHz CMOS UWB front-end receiver. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Zhenghao Lu, Kiat Seng Yeo, Wei Meng Lim, Manh Anh Do, Chirn Chye Boon |
Design of a CMOS Broadband Transimpedance Amplifier With Active Feedback. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Ali Meaamar, Chirn Chye Boon, Kiat Seng Yeo, Manh Anh Do |
A Wideband Low Power Low-Noise Amplifier in CMOS Technology. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Aaron V. T. Do, Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Alper Cabuk |
An Energy-Aware CMOS Receiver Front End for Low-Power 2.4-GHz Applications. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo, Chirn Chye Boon, Wei Meng Lim |
Design and Analysis of Ultra Low Power True Single Phase Clock CMOS 2/3 Prescaler. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Manthena Vamshi Krishna, Xuan Jie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do |
A 1.8-V 3.6-mW 2.4-GHz Fully Integrated CMOS Frequency Synthesizer for the IEEE 802.15.4. |
VLSI-SoC (Selected Papers) |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Aaron V. T. Do, Chirn Chye Boon, Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo |
A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole. |
VLSI-SoC (Selected Papers) |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Manthena Vamshi Krishna, J. Xie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do |
A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Aaron V. T. Do, Chirn Chye Boon, Manh Anh Do, Kiat Seng Yeo, Alper Cabuk |
A 1-V CMOS ultralow-power receiver front end for the IEEE 802.15.4 standard using tuned passive mixer output pole. |
VLSI-SoC |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Xiaomeng Shi, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li |
Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Shan Jiang, Manh Anh Do, Kiat Seng Yeo, Wei Meng Lim |
An 8-bit 200-MSample/s Pipelined ADC With Mixed-Mode Front-End S/H Circuit. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Xiaomeng Shi, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do |
Distortion of pulsed signals in carbon nanotube interconnects. |
Microelectronics Journal |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | J. J. Liu, Manh Anh Do, X. P. Yu, Kiat Seng Yeo, Shan Jiang, Jianguo Ma |
Cmos Even Harmonic Switching mixer for Direct Conversion Receivers. |
Journal of Circuits, Systems, and Computers |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo |
A New Phase Noise Model for TSPC based divider. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Shan Jiang, Manh Anh Do, Kiat Seng Yeo |
A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | X. P. Yu, Manh Anh Do, Lin Jia, Jianguo Ma, Kiat Seng Yeo |
Design of a low power wide-band high resolution programmable frequency divider. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Xiaomeng Shi, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do, Erping Li |
Equivalent circuit model of on-wafer CMOS interconnects for RFICs. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Wei Meng Lim, Han Guo Ma, Manh Anh Do, Kiat Seng Yeo |
A 5GHz to 6GHz integrated differential LNA. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Lin Jia, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do |
A novel methodology for the design of LC tank VCO with low phase noise. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | X. P. Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo |
A new 5 GHz CMOS dual-modulus prescaler. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
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| 1 | Beng Hwee Ong, Choon Beng Sia, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li |
Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling. |
SLIP |
2004 |
DBLP DOI BibTeX RDF |
distributed effects, frequency dependence elements, physical model, skin effects |
Displaying result #1 - #22 of 22 (100 per page; Change: )
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