Search results for "Marc Renaudin"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Tiempo Sas, Gilles Sicard	40nm CMOS 0.35V-Optimized Standard Cell Libraries for Ultra-Low Power Applications.	ACM Trans. Design Autom. Electr. Syst.	2011	DBLP DOI BibTeX RDF
1	Gaetan Canivet, Paolo Maistri, Régis Leveugle, Jessy Clédière, Florent Valette, Marc Renaudin	Glitch and Laser Fault Attacks onto a Secure AES Implementation on a SRAM-Based FPGA.	J. Cryptology	2011	DBLP DOI BibTeX RDF
1	Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin	A Secure Asynchronous FPGA Architecture, Experimental Results and Some Debug Feedback	CoRR	2011	DBLP BibTeX RDF
1	Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis	Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies.	Microelectronics Reliability	2010	DBLP DOI BibTeX RDF
1	Marc Renaudin	ASTEC: Asynchronous Technology for Low Power and Secured Embedded Systems.	PATMOS	2010	DBLP DOI BibTeX RDF
1	Gaetan Canivet, Paolo Maistri, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin	Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGA.	ASAP	2010	DBLP DOI BibTeX RDF
1	Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin	Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Rodrigo Possamai Bastos, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis	Evaluating transient-fault effects on traditional C-element's implementations.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Saeed Mian Qaisar, Laurent Fesquet, Marc Renaudin	Adaptive Rate Sampling and Filtering Based on Level Crossing Sampling.	EURASIP J. Adv. Sig. Proc.	2009	DBLP DOI BibTeX RDF
1	Jeremie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin	Constrained Asynchronous Ring Structures for Robust Digital Oscillators.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Fady Abouzeid, Sylvain Clerc, Fabian Firmin, Marc Renaudin, Gilles Sicard	A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications.	ISLPED	2009	DBLP DOI BibTeX RDF	bose choudhury hocquenghem, design, low power, methodology, logic, energy, cmos, library, circuit, subthreshold, ultra low voltage
1	Gaetan Canivet, Régis Leveugle, Jessy Clédière, Frédéric Valette, Marc Renaudin	Characterization of Effective Laser Spots during Attacks in the Configuration of a Virtex-II FPGA.	VTS	2009	DBLP DOI BibTeX RDF
1	Rodrigo Possamai Bastos, Yannick Monnet, Gilles Sicard, Fernanda Lima Kastensmidt, Marc Renaudin, Ricardo Reis	Comparing transient-fault effects on synchronous and on asynchronous circuits.	IOLTS	2009	DBLP DOI BibTeX RDF
1	Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin	Physical Design of FPGA Interconnect to Prevent Information Leakage.	ARC	2008	DBLP DOI BibTeX RDF
1	Gaetan Canivet, Jessy Clédière, Jean Baptiste Ferron, Frédéric Valette, Marc Renaudin, Régis Leveugle	Detailed Analyses of Single Laser Shot Effects in the Configuration of a Virtex-II FPGA.	IOLTS	2008	DBLP DOI BibTeX RDF
1	Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon	Parallel Asynchronous Watershed Algorithm-Architecture.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	Asynchronous algorithm-architecture, performance evaluation, image segmentation, hill-climbing, correctness proof, parallel processors, watershed
1	N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin	FPGA Architecture for Multi-Style Asynchronous Logic	CoRR	2007	DBLP BibTeX RDF
1	G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain	DPA on quasi delay insensitive asynchronous circuits: formalization and improvement	CoRR	2007	DBLP BibTeX RDF
1	J. Fragoso, Gilles Sicard, Marc Renaudin	Estimation rapide du couple énergie/délai des circuits asynchrones QDI.	Technique et Science Informatiques	2007	DBLP BibTeX RDF
1	Sylvain Miermont, Pascal Vivet, Marc Renaudin	A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling.	PATMOS	2007	DBLP DOI BibTeX RDF
1	Cedric Koch-Hofer, Marc Renaudin, Yvain Thonnart, Pascal Vivet	ASC, a SystemC Extension for Modeling Asynchronous Systems, and Its Application to an Asynchronous NoC.	NOCS	2007	DBLP DOI BibTeX RDF
1	Mischa Dohler, Dominique Barthel, Florence Maraninchi, Laurent Mounier, Stephane Aubert, Christophe Dugas, Aurélien Buhrig, Franck Paugnat, Marc Renaudin, Andrzej Duda, Martin Heusse, Fabrice Valois	The ARESA Project: Facilitating Research, Development and Commercialization of WSNs.	SECON	2007	DBLP DOI BibTeX RDF
1	Julien Goulier, Eric André, Marc Renaudin	A new analytical approach of the impact of jitter on continuous time delta sigma converters.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Cedric Koch-Hofer, Marc Renaudin	Timed Asynchronous Circuits Modeling using SystemC.	FDL	2007	DBLP BibTeX RDF
1	Yannick Monnet, Marc Renaudin, Régis Leveugle	Formal Analysis of Quasi Delay Insensitive Circuits Behavior in the Presence of SEUs.	IOLTS	2007	DBLP DOI BibTeX RDF
1	David Rios-Arambula, Aurélien Buhrig, Gilles Sicard, Marc Renaudin	On the Use of Feedback Systems to Dynamically Control the Supply Voltage of Low-Power Circuits.	J. Low Power Electronics	2006	DBLP DOI BibTeX RDF
1	Yannick Monnet, Marc Renaudin, Régis Leveugle	Designing Resistant Circuits against Malicious Faults Injection Using Asynchronous Logic.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	quasi-delay insensitive, hardening techniques, Asynchronous circuits, data encryption standard, fault attacks
1	Eslam Yahya, Marc Renaudin	QDI Latches Characteristics and Asynchronous Linear-Pipeline Performance Analysis.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin	State-holding in Look-Up Tables: application to asynchronous logic.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin	Security evaluation of dual rail logic against DPA attacks.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	D. Caucheteux, Edith Beigné, Elisabeth Crochon, Marc Renaudin	AsyncRFID: Fully Asynchronous Contactless Systems, Providing High Data Rates, Low Power and Dynamic Adaptation.	ASYNC	2006	DBLP DOI BibTeX RDF
1	G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin	Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits.	CHES	2006	DBLP DOI BibTeX RDF	QDI Asynchronous circuits, Path Swapping (PS), Power analysis
1	Yannick Monnet, Marc Renaudin, Régis Leveugle, Christophe Clavier, Pascal Moitrel	Case Study of a Fault Attack on Asynchronous DES Crypto-Processors.	FDTC	2006	DBLP DOI BibTeX RDF
1	Yannick Monnet, Marc Renaudin, Régis Leveugle, Nathalie Feyt, Pascal Moitrel, F. M'Buwa Nzenguet	Practical Evaluation of Fault Countermeasures on an Asynchronous DES Crypto Processor.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Marc Renaudin, Yannick Monnet	Asynchronous Design: Fault Robustness and Security Characteristics.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Laurent Fesquet, Marc Renaudin	A Programmable Logic Architecture for Prototyping Clockless Circuits.	FPL	2005	DBLP BibTeX RDF
1	Jerome Quartana, Salim Renane, Arnaud Baixas, Laurent Fesquet, Marc Renaudin	GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips.	FPL	2005	DBLP BibTeX RDF
1	David Rios-Arambula, Aurélien Buhrig, Marc Renaudin	Power Consumption Reduction Using Dynamic Control of Micro Processor Performance.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Alin Razafindraibe, Michel Robert, Marc Renaudin, Philippe Maurine	A Method to Design Compact Dual-rail Asynchronous Primitives.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Emmanuel Allier, Julien Goulier, Gilles Sicard, A. Dezzani, Eric André, Marc Renaudin	A 120nm low power asynchronous ADC.	ISLPED	2005	DBLP DOI BibTeX RDF	asynchronous technology, level-crossing sampling, analog-to-digital conversion
1	G. Fraidy Bouesse, Marc Renaudin, Gilles Sicard	Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin	Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	Jerome Quartana, Laurent Fesquet, Marc Renaudin	Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	Edith Beigné, Fabien Clermidy, Pascal Vivet, Alain Clouard, Marc Renaudin	An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework.	ASYNC	2005	DBLP DOI BibTeX RDF
1	Yannick Monnet, Marc Renaudin, Régis Leveugle	Asynchronous circuits transient faults sensitivity evaluation.	DAC	2005	DBLP DOI BibTeX RDF	quasi delay insensitive, simulation, fault model, asynchronous circuits, transient fault
1	N. Huot, H. Dubreuil, Laurent Fesquet, Marc Renaudin	FPGA Architecture for Multi-Style Asynchronous Logic.	DATE	2005	DBLP DOI BibTeX RDF
1	G. Fraidy Bouesse, Marc Renaudin, Sophie Dumont, Fabien Germain	DPA on Quasi Delay Insensitive Asynchronous Circuits: Formalization and Improvement.	DATE	2005	DBLP DOI BibTeX RDF
1	Yannick Monnet, Marc Renaudin, Régis Leveugle	Hardening Techniques against Transient Faults for Asynchronous Circuits.	IOLTS	2005	DBLP DOI BibTeX RDF
1	Laurent Fesquet, Jerome Quartana, Marc Renaudin	Asynchronous Systems on Programmable Logic.	ReCoSoC	2005	DBLP BibTeX RDF
1	Dhanistha Panyasak, Gilles Sicard, Marc Renaudin	A current shaping methodology for lowering em disturbances in asynchronous circuits.	Microelectronics Journal	2004	DBLP DOI BibTeX RDF
1	Laurent Fesquet, Mohammed Es Salhiene, Marc Renaudin	La technologie asynchrone au service de la réduction d'énergie dans les systèmes embarqués.	Annales des Télécommunications	2004	DBLP DOI BibTeX RDF
1	Kamel Slimani, Yann Rémond, Gilles Sicard, Marc Renaudin	TAST Profiler and Low Energy Asynchronous Design Methodology.	PATMOS	2004	DBLP DOI BibTeX RDF
1	F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin	Asynchronous FIR Filters: Towards a New Digital Processing Chain.	ASYNC	2004	DBLP DOI BibTeX RDF	Level-crossing sampling, FIR filter, Speech processing, Asynchronous design, Irregular sampling
1	Marc Renaudin, G. Fraidy Bouesse, Ph. Proust, J. P. Tual, Laurent Sourgen, Fabien Germain	High Security Smartcards.	DATE	2004	DBLP DOI BibTeX RDF
1	Yannick Monnet, Marc Renaudin, Régis Leveugle	Asynchronous Circuits Sensitivity to Fault Injection.	IOLTS	2004	DBLP DOI BibTeX RDF
1	Philippe Maurine, Jean-Baptiste Rigaud, G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin	Statistic Implementation of QDI Asynchronous Primitives.	PATMOS	2003	DBLP DOI BibTeX RDF
1	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin	Power/Area Tradeoffs in 1-of-M Parallel-Prefix Asynchronous Adders.	PATMOS	2003	DBLP DOI BibTeX RDF
1	João Leonardo Fragoso, Gilles Sicard, Marc Renaudin	Automatic Generation of 1-of-M QDI Asynchronous Adders.	SBCCI	2003	DBLP DOI BibTeX RDF
1	Dominique Borrione, Menouer Boubekeur, Laurent Mounier, Marc Renaudin, Antoine Sirianni	Validation of asynchronous circuit specifications using IF/CADP.	VLSI-SOC	2003	DBLP BibTeX RDF
1	Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin	A New Class of Asynchronous A/D Converters Based on Time Quantization.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Dominique Borrione, Menouer Boubekeur, Emil Dumitrescu, Marc Renaudin, Jean-Baptiste Rigaud, Antoine Sirianni	An Approach to the Introduction of Formal Validation in an Asynchronous Circuit Design Flow. (PDF / PS)	HICSS	2003	DBLP DOI BibTeX RDF
1	Quoc Thai Ho, Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Robin Rolland	Implementing Asynchronous Circuits on LUT Based FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
1	Mohammed Es Salhiene, Laurent Fesquet, Marc Renaudin	Dynamic Voltage Scheduling for Real Time Asynchronous Systems.	PATMOS	2002	DBLP DOI BibTeX RDF
1	Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard	Low-Power Asynchronous A/D Conversion.	PATMOS	2002	DBLP DOI BibTeX RDF
1	Bruno Galilée, Franck Mamalet, Marc Renaudin, Pierre-Yves Coulon	Watershed parallel algorithm for asynchronous processors array.	ICME	2002	DBLP DOI BibTeX RDF
1	Jean-Baptiste Rigaud, Laurent Fesquet, Marc Renaudin, Jerome Quartana	High-Level Modeling and Design of Asynchronous Arbiters for On-Chip Communication Systems.	DATE	2002	DBLP DOI BibTeX RDF
1	Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin	Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net.	IWLS	2002	DBLP BibTeX RDF
1	Jean-Baptiste Rigaud, Jerome Quartana, Laurent Fesquet, Marc Renaudin	Modeling and Design of Asynchronous Priority Arbiters for On-Chip Communication Systems.	VLSI-SOC	2001	DBLP BibTeX RDF
1	Christian Piguet, Marc Renaudin, Thierry J.-F. Omnés	Low-power systems on chips (SOCs).	DATE	2001	DBLP DOI BibTeX RDF
1	Marc Renaudin, Pascal Vivet, Frédéric Robin	A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation.	ASYNC	1999	DBLP DOI BibTeX RDF
1	Marc Renaudin, Pascal Vivet, Frédéric Robin	ASPRO-216: A Standard-Cell Q.D.I. 16-Bit RISC Asynchronous Microprocessor.	ASYNC	1998	DBLP DOI BibTeX RDF	asynchronous microprocessor, quasi-delay-insensitive circuits, standard-cell asynchronous design
1	Frédéric Robin, Gilles Privat, Marc Renaudin	Asynchronous Relaxation of Morphological Operators: A Joint Algorithm-Architecture Perspective.	IJPRAI	1997	DBLP BibTeX RDF
1	Alain Guyot, Marc Renaudin, Bachar El Hassan, Volker Levering	Self timed division and square-root extraction.	VLSI Design	1996	DBLP DOI BibTeX RDF	self-timed integrated circuit, square-root extraction, mathematical algorithm, logic level, binary notation, iterative methods, design methodology, integrated circuit design, division, dividing circuits, quotient, pipeline arithmetic, pipelined arithmetic, functional blocks
1	Gilles Privat, Frédéric Robin, Marc Renaudin, Bachar El Hassan	A Fine-Grain Asynchronous VLSI Cellular Array Processor Architecture.	ISCAS	1995	DBLP BibTeX RDF
1	Marc Renaudin, Bachar El Hassan	The Design of Fast Asynchronous Adder Structures and their Implementation Using D.C.V.S. Logic.	ISCAS	1994	DBLP BibTeX RDF
1	A. K. Betts, Ivo Bolsens, E. Sicard, Marc Renaudin, A. Johnstone	SMILE: A scalable microcontroller library element.	Microprocessing and Microprogramming	1993	DBLP DOI BibTeX RDF

Publications of "Marc Renaudin" ( http://dblp.L3S.de/Authors/Marc_Renaudin )