Search results for "Marcelo Lubaszewski"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Renato P. Ribas, S. Bavaresco, N. Schuch, Vinicius Callegaro, Marcelo Lubaszewski, André Inácio Reis	Contributions to the evaluation of ensembles of combinational logic gates.	Microelectronics Journal	2011	DBLP DOI BibTeX RDF
1	Caroline Concatto, João Almeida, Guilherme Fachini, Marcos Herve, Fernanda Lima Kastensmidt, Érika F. Cota, Marcelo Lubaszewski	Improving the yield of NoC-based systems through fault diagnosis and adaptive routing.	J. Parallel Distrib. Comput.	2011	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Cristiano Lazzari, Marcelo Lubaszewski, Fernando Gehm Moraes	A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms.	J. Parallel Distrib. Comput.	2011	DBLP DOI BibTeX RDF
1	Marcos Barcellos Hervé, Marcelo de Souza Moraes, Pedro Almeida, Marcelo Lubaszewski, Fernanda Lima Kastensmidt, Érika F. Cota	Functional Test of Mesh-Based NoCs with Deterministic Routing: Integrating the Test of Interconnects and Routers.	J. Electronic Testing	2011	DBLP DOI BibTeX RDF
1	Luiz Fernando Gonçalves, Jefferson Luiz Bosa, Tiago Roberto Balen, Marcelo Lubaszewski, Eduardo Luis Schneider, Renato V. B. Henriques	Fault Detection, Diagnosis and Prediction in Electrical Valves Using Self-Organizing Maps.	J. Electronic Testing	2011	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, César A. M. Marcon, Fernando Gehm Moraes, Marcelo Lubaszewski	Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time.	International Symposium on Rapid System Prototyping	2011	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Luciano Ost, César A. M. Marcon, Fernando Gehm Moraes, Marcelo Lubaszewski	Evaluating energy consumption of homogeneous MPSoCs using spare tiles.	DATE	2011	DBLP BibTeX RDF
1	Gabriel de M. Borges, Luiz Fernando Gonçalves, Tiago R. Balen, Marcelo Lubaszewski	Evaluating the effectiveness of a mixed-signal TMR scheme based on design diversity.	SBCCI	2010	DBLP DOI BibTeX RDF
1	Mariza Botelho, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Érika F. Cota, Luigi Carro	A broad strategy to detect crosstalk faults in network-on-chip interconnects.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Gabriel de M. Borges, Luiz Fernando Gonçalves, Tiago R. Balen, Marcelo Lubaszewski	Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Marcelo Lubaszewski, Érika F. Cota	Special session 12B: Embedded tutorial test and fault tolerance of networks-on-chip.	VTS	2010	DBLP DOI BibTeX RDF
1	Matheus Braga, Érika F. Cota, Fernanda Lima Kastensmidt, Marcelo Lubaszewski	Efficiently using data splitting and retransmission to tolerate faults in networks-on-chip interconnects.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Tiago R. Balen, Marcelo Lubaszewski	Radiation effects on programmable analog devices and mitigation techniques.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Marcelo Lubaszewski, Andrew Richardson, C. C. Su	Guest editorial.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF
1	Luiz Fernando Gonçalves, Jefferson Luiz Bosa, Renato V. B. Henriques, Marcelo Lubaszewski	Design of an embedded system for the proactive maintenance of electrical valves.	SBCCI	2009	DBLP DOI BibTeX RDF	electromechanical systems, novel applications of FPGAs, testability issues, embedded systems
1	Érika F. Cota, Luigi Carro, Felipe Pinto, Ricardo Augusto da Luz Reis, Marcelo Lubaszewski	Resource-and-time-aware test strategy for configurable quaternary logic blocks.	SBCCI	2009	DBLP DOI BibTeX RDF	quaternary logic, test generation, FPGA testing
1	Marcos Herve, Érika F. Cota, Fernanda Lima Kastensmidt, Marcelo Lubaszewski	Diagnosis of interconnect shorts in mesh NoCs.	NOCS	2009	DBLP DOI BibTeX RDF
1	Renato P. Ribas, S. Bavaresco, Marcelo Lubaszewski, André Inácio Reis	Efficient Test Circuit to Qualify Logic Cells.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Marcelo Lubaszewski	Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?	DFT	2009	DBLP DOI BibTeX RDF
1	Caroline Concatto, Pedro Almeida, Fernanda Lima Kastensmidt, Érika F. Cota, Marcelo Lubaszewski, Marcos Herve	Improving yield of torus nocs through fault-diagnosis-and-repair of interconnect faults.	IOLTS	2009	DBLP DOI BibTeX RDF
1	Bozena Kaminska, Marcelo Lubaszewski, José Machado da Silva	Selected Papers from the International Mixed Signals Testing and GHz/Gbps Test Workshop.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Érika F. Cota, Fernanda Gusmão de Lima Kastensmidt, Maico Cassel, Marcos Herve, Pedro Almeida, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski	A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
1	Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta (eds.)	Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008	SBCCI	2008	DBLP BibTeX RDF
1	Felipe Ghellar, Marcelo Lubaszewski	A novel AES cryptographic core highly resistant to differential power analysis attacks.	SBCCI	2008	DBLP DOI BibTeX RDF	dpa, rijndael, isomorphisms, aes
1	Carlos Roberto Moratelli, Felipe Ghellar, Érika F. Cota, Marcelo Lubaszewski	A fault-tolerant, DFA-resistant AES core.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno	Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture	CoRR	2007	DBLP BibTeX RDF
1	Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes	Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.	IET Computers & Digital Techniques	2007	DBLP BibTeX RDF
1	Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell	Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Analog built-in self-test, Transient response analysis, FPAA
1	Marcelo Lubaszewski, Andrew Richardson, C. C. Su	Guest Editorial.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF
1	Érika F. Cota, Fernanda Lima Kastensmidt, Maico Cassel, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski	Redefining and testing interconnect faults in Mesh NoCs.	ITC	2007	DBLP DOI BibTeX RDF
1	Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell	Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Frederico Ferlini, Marcelo Lubaszewski, Fernando Moraes	DfT for the Reuse of Networks-on-Chip as Test Access Mechanism.	VTS	2007	DBLP DOI BibTeX RDF
1	Carlos Roberto Moratelli, Érika F. Cota, Marcelo Lubaszewski	A cryptography core tolerant to DFA fault attacks.	SBCCI	2006	DBLP DOI BibTeX RDF	cryptography, smart cards, fault attacks
1	Margrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski	Using a software testing technique to identify registers for partial scan implementation.	SBCCI	2006	DBLP DOI BibTeX RDF	hardware testing, testability improvement, hardware description language, automatic test generation, partial scan design
1	Margrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes	Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Kees Goossens, Erik Jan Marinissen, Marcelo Lubaszewski, Fernando Moraes	Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell	Functional Test of Field Programmable Analog Arrays.	VTS	2006	DBLP DOI BibTeX RDF	analog built-in self-test, transient response analysis, FPAA
1	Antonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell	Built-in self-test of global interconnects of field programmable analog arrays.	Microelectronics Journal	2005	DBLP DOI BibTeX RDF
1	Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell	Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	FPAA test, Oscillation Test Strategy (OTS), Built-In Self Test (BIST), analog testing
1	Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell	A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	testability evaluation, design-for-test, analog and mixed-signal testing
1	Alexandre M. Amory, Eduardo Wenzel Brião, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes	A scalable test strategy for network-on-chip routers.	ITC	2005	DBLP DOI BibTeX RDF
1	Marcelo de Souza Moraes, Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski	A constraint-based solution for on-line testing of processors embedded in real-time applications.	SBCCI	2005	DBLP DOI BibTeX RDF	test space exploration, real-time systems, embedded processors, on-line testing, software-based self-test
1	Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell	Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays.	VTS	2005	DBLP DOI BibTeX RDF	FPAA testing, Mixed-signal test, interconnect testing, oscillation-based test
1	Alexandre M. Amory, Marcelo Lubaszewski, Fernando Gehm Moraes, Edson I. Moreno	Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.	DATE	2005	DBLP DOI BibTeX RDF
1	Érika F. Cota, Luigi Carro, Marcelo Lubaszewski	Reusing an on-chip network for the test of core-based systems.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	TAM and wrapper design, test reuse, network-on-chip, test scheduling, SoC test, Core-based test
1	Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu	Searching for Global Test Costs Optimization in Core-Based Systems.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	design space exploration, design for test, SOC testing, embedded cores testing
1	Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell	A New FPGA for DSP Applications Integrating BIST Capabilities.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	hardware test, FPGA, digital signal processing, DSP, BIST, reconfigurable architectures
1	Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski	Testing the Configurable Analog Blocks of Field Programmable Analog Arrays.	ITC	2004	DBLP DOI BibTeX RDF
1	Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes	Reducing test time with processor reuse in network-on-chip based systems.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC testing, computer-aided test (CAT), software-based test, network-on-chip, SoC test, core-based test
1	Antonio Andrade Jr., Érika F. Cota, Marcelo Lubaszewski	Improving mixed-signal SOC testing: a power-aware reuse-based approach with analog BIST.	SBCCI	2004	DBLP DOI BibTeX RDF	system-on-chip, BIST, power aware, mixed-signal test
1	Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell	An Approach to the Built-In Self-Test of Field Programmable Analog Arrays.	VTS	2004	DBLP DOI BibTeX RDF
1	Marcelo Lubaszewski, José Luis Huertas	Test and Design-for-Test of Mixed-Signal Integrated Circuits.	IFIP Congress Tutorials	2004	DBLP BibTeX RDF
1	L. Cassol, O. Betat, Luigi Carro, Marcelo Lubaszewski	The SigmaDelta-BIST Method Applied to Analog Filters.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	BIST, analog test, mixed signal testing, sigma-delta modulator
1	Vinícius P. Correia, Marcelo Lubaszewski, André Inácio Reis	SIFU! - A Didactic Stuck-at Fault Simulator.	MSE	2003	DBLP DOI BibTeX RDF
1	Érika F. Cota, Luigi Carro, Flávio Rech Wagner, Marcelo Lubaszewski	Power-aware NoC Reuse on the Testing of Core-based Systems.	ITC	2003	DBLP DOI BibTeX RDF
1	José Vicente Calvano, Marcelo Lubaszewski	Designing for Test Analog Signal Processors for MEMS-Based Inertial Sensors.	IWSOC	2003	DBLP DOI BibTeX RDF
1	Érika F. Cota, Márcio Eduardo Kreutz, Cesar Albenes Zeferino, Luigi Carro, Marcelo Lubaszewski, Altamiro Amadeu Susin	The Impact of NoC Reuse on the Testing of Core-based Systems.	VTS	2003	DBLP DOI BibTeX RDF
1	José Vicente Calvano, Vladimir Castro Alves, Antônio C. Mesquita, Marcelo Lubaszewski	Filters Designed for Testability Wrapped on the Mixed-Signal Test Bus.	VTS	2002	DBLP DOI BibTeX RDF	BIST, design for test, analog test, mixed-signal test
1	Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu	Test Planning and Design Space Exploration in a Core-Based Environment.	DATE	2002	DBLP DOI BibTeX RDF
1	Renato P. Ribas, André Inácio Reis, Marcelo Lubaszewski	Concepção de Circuitos e Sistemas Integrados.	RITA	2001	DBLP BibTeX RDF
1	Érika F. Cota, Fernanda Lima, Sana Rezgui, Luigi Carro, Raoul Velazco, Marcelo Lubaszewski, Ricardo Reis	Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	integrated circuits radiation effects, aerospace testing, built-in-testing, microprocessor testing
1	José Vicente Calvano, Antonio Carneiro de Mesquita Filho, Vladimir Castro Alves, Marcelo Lubaszewski	Fault Models and Test Generation for OpAmp Circuits - The FFM.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	test generation, fault model, analog test, operational amplifiers
1	Marcelo Lubaszewski, Víctor H. Champac	Guest Editorial.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF
1	Luigi Carro, André C. Nácul, Daniel Janner, Marcelo Lubaszewski	Built-in Test of Analog Non-Linear Circuits in a SOC Environment.	VLSI-SOC	2001	DBLP BibTeX RDF
1	Marcelo Lubaszewski, Salvador Mir, Vladimir Kolarik, C. Nielsen, Bernard Courtois	Design of self-checking fully differential circuits and boards.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
1	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Testing a PWM circuit using functional fault models and compact test vectors for operational amplifiers.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	PWM circuit, compact test vectors, analog VLSI technology, functional fault macromodels, compact test vector construction, open loop gain, CMMR, analog circuit simulation complexity, VLSI, integrated circuit testing, design for testability, automatic test pattern generation, fault modeling, fault simulation, fault simulation, operational amplifiers, operational amplifiers, test pattern, functional fault models, analogue circuits, fault dictionary, pulse width modulation, slew-rate
1	Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell	TI-BIST: a temperature independent analog BIST for switched-capacitor filters.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	temperature independent analog BIST, simulation, built-in self test, BIST, analogue circuits, switched capacitor filters, switched-capacitor filters, analog BIST
1	José Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski	Fault Detection Methodology and BIST Method for 2nd Order Butterworth, Chebyshev and Bessel Filter Approximations.	VTS	2000	DBLP DOI BibTeX RDF	BIST, Analog Test, Transient Analysis
1	Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski	Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte.	DATE	2000	DBLP DOI BibTeX RDF
1	Benoît Charlot, Salvador Mir, Érika F. Cota, Marcelo Lubaszewski, Bernard Courtois	Fault modeling of suspended thermal MEMS.	ITC	1999	DBLP DOI BibTeX RDF
1	Bernard Courtois, Jean-Michel Karam, Salvador Mir, Marcelo Lubaszewski, Vladimir Székely, Márta Rencz, Klaus Hofmann, Manfred Glesner	Design and Test of MEMs.	VLSI Design	1999	DBLP BibTeX RDF
1	Érika F. Cota, Luigi Carro, Marcelo Lubaszewski	A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester.	DATE	1999	DBLP DOI BibTeX RDF
1	Marcelo Lubaszewski, Bernard Courtois	A Reliable Fail-Safe System.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	reliability, built-in self-test, concurrent error detection, Self-checking, fail-safe
1	Vladimir Székely, Márta Rencz, Jean-Michel Karam, Marcelo Lubaszewski, Bernard Courtois	Thermal Monitoring of Self-Checking Systems.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	self-checking circuits, thermal testing, temperature sensors, thermal sensors
1	Marcelo Lubaszewski	Bridging the Gap between Microelectronics and Micromechanics Testing. (PDF / PS)	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Jaime Velasco-Medina, Marcelo Lubaszewski, Michael Nicolaidis	An Approach to the On-Line Testing of Operational Amplifiers.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Jean-Michel Karam, Marcelo Lubaszewski, S. Blanton, Andrew Richardson	Testing MEMS. (PDF / PS)	VTS	1998	DBLP DOI BibTeX RDF
1	Marcelo Lubaszewski, Érika F. Cota, Bernard Courtois	Microsystems Testing: an Approach and Open Problems.	DATE	1998	DBLP DOI BibTeX RDF	Microsystem Testing, Analog Fault Model, CAT
1	Érika F. Cota, José Di Elias Domênico, Marcelo Lubaszewski	A CAT Tool for Frequency-domain Testing and Diagnosis on Analog.	J. Braz. Comp. Soc.	1997	DBLP BibTeX RDF
1	Salvador Mir, Marcelo Lubaszewski, Bernard Courtois	Unified built-in self-test for fully differential analog circuits.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	on-line/off-line analog test, unified BIST, fully differential analog circuits, common-mode feedback, analog BIST
1	Salvador Mir, Marcelo Lubaszewski, Bernard Courtois	Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	analog ATPG, fault diagnosis, fault-based testing, analog BIST
1	Vladimir Székely, Márta Rencz, Jean-Michel Karam, Marcelo Lubaszewski, Bernard Courtois	Thermal Monitoring Of Safety-Critical Integrated Systems.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
1	Marcelo Lubaszewski, Salvador Mir, Leandro Pulz	ABILBO: Analog BuILt-in Block Observer.	ICCAD	1996	DBLP DOI BibTeX RDF	built-in self-test, design for test, analog and mixed-signal testing
1	Vladimir Kolarik, Salvador Mir, Marcelo Lubaszewski, Bernard Courtois	Analog checkers with absolute and relative tolerances.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Khaled Saab, Bozena Kaminska, Bernard Courtois, Marcelo Lubaszewski	Frequency-based BIST for analog circuit testin.	VTS	1995	DBLP DOI BibTeX RDF	waveform generators, frequency-based BIST, analog circuit testing, sine wave generator, sinusoidal input signals, variable frequency input stimulus, frequency input signal, T-BIST approach, frequency-counter BIST approach, VLSI, VLSI, built-in self test, integrated circuit testing, analogue integrated circuits
1	Salvador Mir, Vladimir Kolarik, Marcelo Lubaszewski, C. Nielsen, Bernard Courtois	Built-in self-test and fault diagnosis of fully differential analogue circuits.	ICCAD	1994	DBLP DOI BibTeX RDF
1	Meryem Marzouki, Marcelo Lubaszewski, Mohamed Hedi Touati	Unifying test and diagnosis of interconnects and logic clusters in partial boundary scan boards.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Marcelo Lubaszewski, Bernard Courtois	On the Design of Self-Checking Boundary Scannable Boards.	ITC	1992	DBLP DOI BibTeX RDF

Publications of "Marcelo Lubaszewski" ( http://dblp.L3S.de/Authors/Marcelo_Lubaszewski )