Search results for "Maria K. Michael"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Stelios Neophytou, Maria K. Michael	Test Pattern Generation of Relaxed n-Detect Test Sets.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Christos Ttofis, Theocharis Theocharides, Maria K. Michael	FPGA-Based Laboratory Assignments for NoC-Based Manycore Systems.	IEEE Trans. Education	2012	DBLP DOI BibTeX RDF
1	Christos Ttofis, Agathoklis Papadopoulos, Theocharis Theocharides, Maria K. Michael, Demosthenes Doumenis	An MPSoC-Based QAM Modulation Architecture with Run-Time Load-Balancing.	EURASIP J. Emb. Sys.	2011	DBLP DOI BibTeX RDF
1	Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael	Improved diagnosis using enhanced fault dominance.	Integration	2011	DBLP DOI BibTeX RDF
1	Stelios Neophytou, Kyriakos Christou, Maria K. Michael	An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration.	European Test Symposium	2011	DBLP DOI BibTeX RDF	zero-supressed binary decision diagrams, digital circuits, path similarity
1	Agathoklis Papadopoulos, Theocharis Theocharides, Maria K. Michael	Towards optimal CMOS lifetime via unified reliability modeling and multi-objective optimization.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar	Hardware-Enabled Dynamic Resource Allocation for Manycore Systems Using Bidding-Based System Feedback.	EURASIP J. Emb. Sys.	2010	DBLP DOI BibTeX RDF
1	Stelios Neophytou, Maria K. Michael	Test Set Generation with a Large Number of Unspecified Bits Using Static and Dynamic Techniques.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	VLSI, test generation, Reliability and testing
1	Christos Ttofis, Agathoklis Papadopoulos, Theocharis Theocharides, Maria K. Michael, Demosthenes Doumenis	A reconfigurable MPSoC-based QAM modulation architecture.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Kyriakos Christou, Maria K. Michael, Stelios Neophytou	Identification of critical primitive path delay faults without any path enumeration.	VTS	2010	DBLP DOI BibTeX RDF
1	Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar	Towards embedded runtime system level optimization for MPSoCs: on-chip task allocation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	vlsi design, task allocation, multiprocessor systems-on-chip
1	Stelios Neophytou, Maria K. Michael, Kyriakos Christou	Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning.	DFT	2009	DBLP DOI BibTeX RDF
1	Kyriakos Christou, Maria K. Michael, Spyros Tragoudas	On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Zero-suppressed binary decision diagram, Irredundant sum-of-products, Critical path delay faults, Compact test generation, Delay testing, Path delay faults
1	Stelios Neophytou, Maria K. Michael	Two New Methods for Accurate Test Set Relaxation via Test Set Replacement.	ISQED	2008	DBLP DOI BibTeX RDF	Test Set Relaxation, Test Generation
1	Theocharis Theocharides, Maria K. Michael, Marios M. Polycarpou, Ajit Dingankar	A Novel System-Level On-Chip Resource Allocation Method for Manycore Architectures.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Paolo Bernardi, Kyriakos Christou, Michelangelo Grosso, Maria K. Michael, Ernesto Sánchez, Matteo Sonza Reorda	Exploiting MOEA to Automatically Geneate Test Programs for Path-Delay Faults in Microprocessors.	EvoWorkshops	2008	DBLP DOI BibTeX RDF	microprocessor, BDD, MOEA, path-delay testing
1	Kyriakos Christou, Maria K. Michael, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda	A Novel SBST Generation Technique for Path-Delay Faults in Microprocessors Exploiting Gate- and RT-Level Descriptions.	VTS	2008	DBLP DOI BibTeX RDF	SBST, path-delay faults, microprocessor test
1	Stelios Neophytou, Maria K. Michael	On the Relaxation of n-detect Test Sets.	VTS	2008	DBLP DOI BibTeX RDF	N-detect, test set relaxation
1	Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael	Accelerating Diagnosis via Dominance Relations between Sets of Faults.	VTS	2007	DBLP DOI BibTeX RDF
1	Stelios Neophytou, Maria K. Michael	Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified Bits.	DFT	2007	DBLP DOI BibTeX RDF
1	Stelios Neophytou, Maria K. Michael, Spyros Tragoudas	Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael	Evaluation of Collapsing Methods for Fault Diagnosis.	ISQED	2006	DBLP DOI BibTeX RDF
1	Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael	Sub-faults identification for collapsing in diagnosis.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Kyriakos Christou, Maria K. Michael, Spyros Tragoudas	Implicit Critical PDF Test Generation with Maximal Test Efficiency.	DFT	2006	DBLP DOI BibTeX RDF
1	Stelios Neophytou, Maria K. Michael, Spyros Tragoudas	Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding.	IOLTS	2006	DBLP DOI BibTeX RDF
1	Maria K. Michael, Spyros Tragoudas	Function-based compact test pattern generation for path delay faults.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Maria K. Michael, Stelios Neophytou, Spyros Tragoudas	Functions for Quality Transition Fault Tests.	ISQED	2005	DBLP DOI BibTeX RDF
1	Stelios Neophytou, Maria K. Michael, Spyros Tragoudas	Test set enhancement for quality transition faults using function-based methods.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	high quality test, ATPG, delay test, critical paths, transition fault, test compaction
1	Maria K. Michael, Kyriakos Christou, Spyros Tragoudas	Towards finding path delay fault tests with high test efficiency using ZBDDs.	ICCD	2005	DBLP DOI BibTeX RDF
1	Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas	A unified framework for generating all propagation functions for logic errors and events.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas	Exact path delay fault coverage with fundamental ZBDD operations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Maria K. Michael, Spyros Tragoudas	Generation of Hazard Identification Functions.	ISQED	2003	DBLP DOI BibTeX RDF
1	Maria K. Michael, Spyros Tragoudas	ATPG tools for delay faults at the functional level.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing
1	Maria K. Michael, Spyros Tragoudas	ATPG for Path Delay Faults without Path Enumeration.	ISQED	2001	DBLP DOI BibTeX RDF
1	Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas	Exact path delay grading with fundamental BDD operations.	ITC	2001	DBLP DOI BibTeX RDF
1	Spyros Tragoudas, Maria K. Michael	Functional ATPG for Delay Faults.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
1	Spyros Tragoudas, Maria K. Michael	ATPG Tools for Delay Faults at the Functional Level.	DATE	1999	DBLP DOI BibTeX RDF

Publications of "Maria K. Michael" ( http://dblp.L3S.de/Authors/Maria_K._Michael )