| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou |
Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger |
Resonant clock design for a power-efficient high-volume x86-64 microprocessor. |
ISSCC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Arun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin |
Computational sprinting. |
HPCA |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Hsiang Ma, Jerry C. Kao, Marios C. Papaefthymiou |
A 5.5GS/s 28mW 5-bit flash ADC with resonant clock distribution. |
ESSCIRC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou |
187 MHz Subthreshold-Supply Charge-Recovery FIR. |
J. Solid-State Circuits |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Xun Liu, Yuantao Peng, Marios C. Papaefthymiou |
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Zhengtao Yu 0002, Marios C. Papaefthymiou, Xun Liu |
Skew spreading for peak current reduction. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
low power, clock skew, clock scheduling |
| 1 | Xun Liu, Yuantao Peng, Marios C. Papaefthymiou |
Practical repeater insertion for low power: what repeater library do we need? |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiyoun Kim, Marios C. Papaefthymiou, José Neves |
Parallelizing post-placement timing optimization. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou |
Charge-Recovery Computing on Silicon. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
Energy-recovering circuits, resonant systems, energy efficient computing, voltage scaling, reversible logic, adiabatic computing |
| 1 | Xun Liu, Marios C. Papaefthymiou |
HyPE: hybrid power estimation for IP-based systems-on-chip. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler |
Boost Logic: A High Speed Energy Recovery Circuit Family. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler |
Two-Phase Resonant Clock Distribution. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler |
A GHz-class charge recovery logic. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
resonant systems, energy recovery, adiabatic |
| 1 | Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou |
Fast, efficient, recovering, and irreversible. |
Conf. Computing Frontiers |
2005 |
DBLP DOI BibTeX RDF |
charge-recovery circuits, resonant systems, reversible logic, adiabatic computing |
| 1 | Xun Liu, Yuantao Peng, Marios C. Papaefthymiou |
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiyoun Kim, José Neves, Marios C. Papaefthymiou |
Multi-Session Partitioning for Parallel Timing Optimization. |
PDCAT |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Xun Liu, Marios C. Papaefthymiou |
A Markov chain sequence generator for power macromodeling. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou |
Experimental Evaluation of Resonant Clock Distribution. |
ISVLSI |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Joohee Kim, Marios C. Papaefthymiou |
Constant-load energy recovery memory for efficient high-speed operation. |
ISLPED |
2004 |
DBLP DOI BibTeX RDF |
adiabatic circuitry, charge recovery, cache memories, on-chip memories, low-power computing, low-energy design |
| 1 | Jiyoun Kim, Marios C. Papaefthymiou, Athar B. Tayyab |
An Algorithm for Geometric Load Balancing with Two Constraints. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Xun Liu, Yuantao Peng, Marios C. Papaefthymiou |
Practical repeater insertion for low power: what repeater library do we need? |
DAC |
2004 |
DBLP DOI BibTeX RDF |
low power, interconnect, repeater insertion |
| 1 | Juang-Ying Chueh, Conrad H. Ziesler, Marios C. Papaefthymiou |
Empirical evaluation of timing and power in resonant clock distribution. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou |
Fine-grain real-time reconfigurable pipelining. |
IBM Journal of Research and Development |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou |
A true single-phase energy-recovery multiplier. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Joohee Kim, Marios C. Papaefthymiou |
Block-based multiperiod dynamic memory design for low data-retention power. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Xun Liu, Marios C. Papaefthymiou |
Design of a 20-mb/s 256-state Viterbi decoder. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Conrad H. Ziesler, Joohee Kim, Marios C. Papaefthymiou |
Energy Recovering ASIC Design. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou |
A 225 MHz resonant clocked ASIC chip. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
adiabatic logic, resonant LC tank, single phase, VLSI, CMOS, flip-flop, low energy, clock generator |
| 1 | Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman |
Reduced Delay Uncertainty in High Performance Clock Distribution Networks. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman |
Retiming and clock scheduling for digital circuit optimization. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Joohee Kim, Conrad H. Ziesler, Marios C. Papaefthymiou |
Energy recovering static memory. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
adiabatic circuitry, charge recovery, cache memories, on-chip memories, low-power computing, low-energy design |
| 1 | Xun Liu, Marios C. Papaefthymiou |
Design of a high-throughput low-power IS95 Viterbi decoder. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
bus reduction, communications, pipelining |
| 1 | Xun Liu, Marios C. Papaefthymiou |
Incorporation of input glitches into power macromodeling. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Xun Liu, Marios C. Papaefthymiou |
A Markov chain sequence generator for power macromodeling. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Farinaz Koushanfar, Darko Kirovski, Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou |
Symbolic debugging of embedded hardware and software. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Suhwan Kim, Marios C. Papaefthymiou |
True single-phase adiabatic circuitry. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou |
Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier. |
ARVLSI |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou |
A resonant clock generator for single-phase adiabatic systems. |
ISLPED |
2001 |
DBLP DOI BibTeX RDF |
SCAL, SCAL-D, TSEL, adiabatic logic, dynamic circuitry, single phase, VLSI, CMOS, low energy, resonant, clock generator |
| 1 | Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou |
A True Single-Phase 8-bit Adiabatic Multiplier. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Xun Liu, Marios C. Papaefthymiou |
A static power estimation methodolodgy for IP-based design. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou |
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak |
Optimizing computations for effective block-processing. |
ACM Trans. Design Autom. Electr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
computation dataflow graphs, scheduling, embedded systems, combinatorial optimization, high-level synthesis, vectorization, integer linear programming, retiming |
| 1 | Joohee Kim, Marios C. Papaefthymiou |
Dynamic Memory Design for Low Data-Retention Power. |
PATMOS |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Inki Hong, Darko Kirovski, Miodrag Potkonjak, Marios C. Papaefthymiou |
Symbolic debugging of globally optimized behavioral specifications. |
ASP-DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Inki Hong, Miodrag Potkonjak, Marios C. Papaefthymiou |
Efficient Block Scheduling to Minimize Context Switching Time for Programmable Embedded Processors. |
Design Autom. for Emb. Sys. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Suhwan Kim, Marios C. Papaefthymiou |
Single-phase source-coupled adiabatic logic. |
ISLPED |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman |
Maximizing Performance by Retiming and Clock Skew Scheduling. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman |
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Giuseppe Bernacchia, Marios C. Papaefthymiou |
Analytical macromodeling for high-level power estimation. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Suhwan Kim, Marios C. Papaefthymiou |
True single-phase energy-recovering logic for low-power, high-speed VLSI. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Marios C. Papaefthymiou |
Asymptotically efficient retiming under setup and hold constraints. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Kumar N. Lalgudi, Marios C. Papaefthymiou |
Computing Strictly-Second Shortest Paths. |
Inf. Process. Lett. |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Kumar N. Lalgudi, Marios C. Papaefthymiou |
Retiming edge-triggered circuits under general delay models. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Alexander T. Ishii, Charles E. Leiserson, Marios C. Papaefthymiou |
Optimizing two-phase, level-clocked circuitry. |
J. ACM |
1997 |
DBLP DOI BibTeX RDF |
clock tuning, level-clocked circuitry, multiphase clocking, timing analysis and optimization, VLSI, retiming |
| 1 | Fang Wang, Marios C. Papaefthymiou, Mark S. Squillante |
Performance Evaluation of Gang Scheduling for Parallel and Distributed Multiprogramming. |
JSSPP |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou |
Stochastic Analysis of Gang Scheduling in Parallel and Distributed Systems. |
Perform. Eval. |
1996 |
DBLP BibTeX RDF |
|
| 1 | Marios C. Papaefthymiou, Kumar N. Lalgudi |
Fixed-phase retiming for low power design. |
ISLPED |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Kumar N. Lalgudi, Marios C. Papaefthymiou, Miodrag Potkonjak |
Optimizing Systems for Effective Block-Processing: The k-Delay Problem. |
DAC |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark S. Squillante, Fang Wang, Marios C. Papaefthymiou |
An Analysis of Gang Scheduling for Multiprogrammed Parallel Computing Environments. |
SPAA |
1996 |
DBLP BibTeX RDF |
|
| 1 | Fang Wang, Hubertus Franke, Marios C. Papaefthymiou, Pratap Pattnaik, Larry Rudolph, Mark S. Squillante |
A Gang Scheduling Design for Multiprogrammed Parallel Computing Environments. |
JSSPP |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Kumar N. Lalgudi, Marios C. Papaefthymiou |
Efficient retiming under a general delay model. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
retiming algorithm, general delay model, edge-triggered circuits, load-dependent gate delays, register delays, integer linear programming constraints, integer phonotonic programming formulation, linear programming, delays, timing, integer programming, logic design, logic design, logic circuits, clock skew, propagation delays, interconnect delays |
| 1 | Kumar N. Lalgudi, Marios C. Papaefthymiou |
DELAY: An Efficient Tool for Retiming with Realistic Delay Modeling. |
DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou |
Precomputation-based sequential logic optimization for low power. |
IEEE Trans. VLSI Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Marios C. Papaefthymiou |
Understanding Retiming Through Maximum Avarage-Delay Cycles. |
Mathematical Systems Theory |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Anant Agarwal, John V. Guttag, Christoforos N. Hadjicostis, Marios C. Papaefthymiou |
Memory Assignment for Multiprocessor Caches through Grey Coloring. |
PARLE |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou |
Precomputation-based sequential logic optimization for low power. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Marios C. Papaefthymiou, Keith H. Randall |
TIM: A Timing Package for Two-Phase, Level-Clocked Circuitry. |
DAC |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Marios C. Papaefthymiou |
Understanding Retiming Through Maximum Average-Weight Cycles. |
SPAA |
1991 |
DBLP DOI BibTeX RDF |
|
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