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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 14 occurrences of 14 keywords
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Results
Found 30 publication records. Showing 30 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Pedro Echeverría, Marisa López-Vallejo |
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs.  |
Microprocessors and Microsystems - Embedded Hardware Design  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Ignacio Herrera-Alzu, Marisa López-Vallejo |
Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs. |
PATMOS |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Pablo Ituero, Marisa López-Vallejo, M. A. S. Marcos, Carlos Gómez Osuna |
On-chip Monitoring: A Light-Weight Interconnection Network Approach. |
DSD |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | José Luis Ayala, Cándido Méndez, Marisa López-Vallejo |
Thermal analysis and modeling of embedded processors. |
Computers & Electrical Engineering |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Pedro Echeverría, Marisa López-Vallejo, Walter Bolognesi, Carlos A. López-Barrio |
Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs. |
ICECS |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Pedro Echeverría Aramendi, José L. Ayala, Marisa López-Vallejo |
Power Considerations in Banked CAMs: A Leakage Reduction Approach. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | José Luis Ayala, Marisa López-Vallejo, Carlos A. López-Barrio, Alexander V. Veidenbaum |
A hardware mechanism to reduce the energy consumption of the register file of in-order architectures. |
IJES |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | David Atienza, Praveen Raghavan, José Luis Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo |
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures. |
Integration |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Angel Fernandez Herrero, Ignacio Elguezábal, Marisa López-Vallejo |
A Web-Based Environment Providing Remote Access To FPGA Platforms For Teaching Digital Hardware Design. |
e-Learning |
2008 |
DBLP BibTeX RDF |
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| 1 | Miguel Angel Sánchez, Pedro Echeverría, Francisco Mansilla, Marisa López-Vallejo |
Designing Highly Parameterized Hardware using xHdl. |
FDL |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk |
An FPGA run-time parameterisable Log-Normal Random Number Generator. |
ARC |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | José L. Ayala, Marisa López-Vallejo, David Atienza, Praveen Raghavan, Francky Catthoor, Diederik Verkest |
Energy-aware compilation and hardware design for VLIW embedded systems. |
IJES |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | José Luis Ayala, Anya Apavatjrut, David Atienza, Marisa López-Vallejo, Carlos A. López-Barrio |
Thermal Characterization and Thermal Management in Processor-Based Systems. |
Power-aware Computing Systems |
2007 |
DBLP BibTeX RDF |
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| 1 | Praveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo |
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Pablo Ituero, José L. Ayala, Marisa López-Vallejo |
Leakage-based On-Chip Thermal Sensor for CMOS Technology. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Pablo Ituero, Gorka Landaburu, Javier Del Ser, Marisa López-Vallejo, Pedro M. Crespo, Vicente Atxa, Jon Altuna |
Joint Source-Channel Decoding ASIP Architecture for Sensor Networks. |
ICESS |
2007 |
DBLP DOI BibTeX RDF |
DSC, Sensor Networks, VLIW, ASIP, Turbo Codes, Joint Source-Channel Coding, Factor Graphs |
| 1 | David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo |
Compiler-Driven Leakage Energy Reduction in Banked Register Files. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Pablo Ituero, Marisa López-Vallejo |
New Schemes in Clustered VLIW Processors Applied to Turbo Decoding. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | José Luis Ayala, Marisa López-Vallejo |
Integrating functional and power simulation in embedded systems design. |
J. Embedded Computing |
2005 |
DBLP BibTeX RDF |
|
| 1 | José Luis Ayala, Marisa López-Vallejo |
Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems. |
Power-aware Computing Systems |
2005 |
DBLP BibTeX RDF |
|
| 1 | José L. Ayala, Alexander V. Veidenbaum, Marisa Luisa López-Vallejo |
Power-Aware Compilation for Register File Energy Reduction. |
International Journal of Parallel Programming |
2003 |
DBLP DOI BibTeX RDF |
register file management, compiler support, energy aware |
| 1 | Marisa Luisa López-Vallejo, Juan Carlos López |
On the hardware-software partitioning problem: System modeling and partitioning techniques. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
general optimization procedures, clustering, fuzzy logic, expert systems, system modeling, cost functions, Hardware-software co-design, hardware-software partitioning |
| 1 | José L. Ayala, Marisa Luisa López-Vallejo |
A Unified Framework for Power-Aware Design of Embedded Systems. |
PATMOS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez |
Energy Aware Register File Implementation through Instruction Predecode. |
ASAP |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Antonio G. Lomeña, Marisa Luisa López-Vallejo, Yosinori Watanabe, Alex Kondratyev |
An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Marisa Luisa López-Vallejo, J. M. Fernández Freire, J. Colás |
ED68K. A design framework for the development of digital systems based on MC68000. |
Computers and Education. Towards an Interconnected Society |
2001 |
DBLP BibTeX RDF |
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| 1 | Marisa Luisa López-Vallejo, Jesús Grajal, Juan Carlos López |
Constraint-Driven System Partitioning. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Marisa Luisa López-Vallejo, Juan Carlos López, Carlos Angel Iglesias |
Hardware-Software Partitioning at the Knowledge Level. |
Appl. Intell. |
1999 |
DBLP DOI BibTeX RDF |
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| 1 | Marisa Luisa López-Vallejo, Carlos Angel Iglesias, Juan Carlos López |
Applying the Propose&Revise Strategy to the Hardware-Software Partitioning Problem. |
IEA/AIE (Vol. 1) |
1998 |
DBLP DOI BibTeX RDF |
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| 1 | Marisa Luisa López-Vallejo, Carlos Angel Iglesias, Juan Carlos López |
A Knowledge-based System for Hardware-Software Partitioning. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
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