Search results for "Mark Horowitz"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Andrew Danowitz, Kyle Kelley, James Mao, John P. Stevenson, Mark Horowitz	CPU DB: Recording Microprocessor History.	ACM Queue	2012	DBLP DOI BibTeX RDF
1	Gordon Wan, Xiangli Li, Gennadiy Agranov, Marc Levoy, Mark Horowitz	CMOS Image Sensors With Multi-Bucket Pixels for Computational Photography.	J. Solid-State Circuits	2012	DBLP DOI BibTeX RDF
1	Andrew Danowitz, Kyle Kelley, James Mao, John P. Stevenson, Mark Horowitz	CPU DB: recording microprocessor history.	Commun. ACM	2012	DBLP DOI BibTeX RDF
1	Sameh Galal, Mark Horowitz	Energy-Efficient Floating-Point Unit Design.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	Understanding sources of ineffciency in general-purpose chips.	Commun. ACM	2011	DBLP DOI BibTeX RDF
1	Douglas Densmore, Mark Horowitz, Smita Krishnaswamy, Xiling Shen, Adam Arkin, Erik Winfree, Chris Voigt	Joint DAC/IWBDA special session design and synthesis of biological circuits.	DAC	2011	DBLP DOI BibTeX RDF
1	Sangho Youn, Jaeha Kim, Mark Horowitz	Global convergence analysis of mixed-signal systems.	DAC	2011	DBLP DOI BibTeX RDF
1	Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul	Beyond the horizon: The next 10x reduction in power - Challenges and solutions.	ISSCC	2011	DBLP DOI BibTeX RDF
1	Kyle Kelley, Megan Wachs, Andrew Danowitz, P. Stevenson, S. Richardon, Mark Horowitz	Intermediate representations for controllers in chip generators.	DATE	2011	DBLP DOI BibTeX RDF
1	Sameh Galal, Mark Horowitz	Latency Sensitive FMA Design.	IEEE Symposium on Computer Arithmetic	2011	DBLP DOI BibTeX RDF
1	Andrew Adams, David E. Jacobs, Jennifer Dolson, Marius Tico, Kari Pulli, Eino-Ville Talvala, Boris Ajdin, Daniel A. Vaquero, Hendrik P. A. Lensch, Mark Horowitz, Sung Hee Park, Natasha Gelfand, Jongmin Baek, Wojciech Matusik, Marc Levoy	The Frankencamera: an experimental platform for computational photography.	ACM Trans. Graph.	2010	DBLP DOI BibTeX RDF
1	Ofer Shacham, Omid Azizi, Megan Wachs, Stephen Richardson, Mark Horowitz	Rethinking Digital Design: Why Design Must Change.	IEEE Micro	2010	DBLP DOI BibTeX RDF
1	Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	Understanding sources of inefficiency in general-purpose chips.	ISCA	2010	DBLP DOI BibTeX RDF	tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance
1	Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz	Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis.	ISCA	2010	DBLP DOI BibTeX RDF	co-optimization, design trade-offs, optimization, energy efficiency, design space exploration, microarchitecture
1	Mark Horowitz, Metha Jeeradit, Frances Lau, Sabrina Liao, ByongChan Lim, James Mao	Fortifying analog models with equivalence checking and coverage analysis.	DAC	2010	DBLP DOI BibTeX RDF	analog validation, model-first design, design methodology, fault coverage, equivalence checking, formal validation
1	Metha Jeeradit, Jaeha Kim, Mark Horowitz	Intent-leveraged optimization of analog circuits via homotopy.	DATE	2010	DBLP BibTeX RDF
1	Mark Horowitz	Why design must change: Rethinking digital design.	DATE	2010	DBLP BibTeX RDF
1	Omid Azizi, Aqeel Mahesri, John P. Stevenson, Sanjay J. Patel, Mark Horowitz	An integrated framework for joint design space exploration of microarchitecture and circuits.	DATE	2010	DBLP BibTeX RDF
1	Chaomei Chen, Yue Chen, Mark Horowitz, Haiyan Hou, Zeyuan Liu, Donald Pellegrino	Towards an explanatory and computational theory of scientific discovery.	J. Informetrics	2009	DBLP DOI BibTeX RDF
1	Omid Azizi, Aqeel Mahesri, Sanjay J. Patel, Mark Horowitz	Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design.	SIGARCH Computer Architecture News	2009	DBLP DOI BibTeX RDF
1	Chaomei Chen, Yue Chen, Mark Horowitz, Haiyan Hou, Zeyuan Liu, Donald Pellegrino	Towards an explanatory and computational theory of scientific discovery	CoRR	2009	DBLP BibTeX RDF
1	Bita Nezamfar, Mark Horowitz	In field, energy-performance tunable FPGA architectures.	FPL	2009	DBLP DOI BibTeX RDF
1	Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz	A memory system design framework: creating smart memories.	ISCA	2009	DBLP DOI BibTeX RDF	memory access protocol, protocol controller, transactional memory, reconfigurable architecture, cache coherence, memory systems, multi-core processors, stream programming
1	Bita Nezamfar, Mark Horowitz	Energy-performance tunable logic.	CICC	2009	DBLP DOI BibTeX RDF
1	Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz	Using a configurable processor generator for computer architecture prototyping.	MICRO	2009	DBLP DOI BibTeX RDF	computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design
1	Mark Horowitz	Why design must change: rethinking digital design.	MICRO	2009	DBLP DOI BibTeX RDF
1	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparative evaluation of memory models for chip multiprocessors.	TACO	2008	DBLP DOI BibTeX RDF	streaming memory, parallel programming, Chip multiprocessors, cache coherence, locality optimizations
1	Omid Azizi, Jamison D. Collins, Dinesh Patil, Hong Wang 0003, Mark Horowitz	Processor Performance Modeling using Symbolic Simulation.	ISPASS	2008	DBLP DOI BibTeX RDF
1	Robert Kunz, Mark Horowitz	The case for simple, visible cache coherency.	MSPC	2008	DBLP DOI BibTeX RDF	SpecOMP2001, shared-memory multiprocessor, FLASH, coherence protocol, cc-NUMA, software optimization, performance bottlenecks
1	Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz	Verification of chip multiprocessor memory systems using a relaxed scoreboard.	MICRO	2008	DBLP DOI BibTeX RDF
1	Eino-Ville Talvala, Andrew Adams, Mark Horowitz, Marc Levoy	Veiling glare in high dynamic range imaging.	ACM Trans. Graph.	2007	DBLP DOI BibTeX RDF	HDR imaging, structured occlusion mask, veiling glare, global illumination, computational photography
1	Jacob Leverich, Hideho Arakida, Alex Solomatnikov, Amin Firoozshahian, Mark Horowitz, Christos Kozyrakis	Comparing memory systems for chip multiprocessors.	ISCA	2007	DBLP DOI BibTeX RDF	streaming memory, parallel programming, chip multiprocessors, locality optimizations, coherent caches
1	Alex Solomatnikov, Amin Firoozshahian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Zain Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz	Chip Multi-Processor Generator.	DAC	2007	DBLP DOI BibTeX RDF
1	Mark Horowitz	Scaling, Power and the Future of CMOS.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman	Robust Energy-Efficient Adder Topologies.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
1	Marc Levoy, Ren Ng, Andrew Adams, Matthew Footer, Mark Horowitz	Light field microscopy.	ACM Trans. Graph.	2006	DBLP DOI BibTeX RDF	volume rendering, light fields, tomography, deconvolution, microscopy, synthetic aperture
1	Pradeep Sen, Billy Chen, Gaurav Garg, Stephen R. Marschner, Mark Horowitz, Marc Levoy, Hendrik P. A. Lensch	Dual photography.	ACM Trans. Graph.	2005	DBLP DOI BibTeX RDF	dual photography, image synthesis, image-based relighting
1	Bennett Wilburn, Neel Joshi, Vaibhav Vaish, Eino-Ville Talvala, Emilio R. Antúnez, Adam Barth, Andrew Adams, Mark Horowitz, Marc Levoy	High performance imaging using large camera arrays.	ACM Trans. Graph.	2005	DBLP DOI BibTeX RDF	camera arrays, spatiotemporal sampling, synthetic aperture
1	Stephen P. Boyd, Seung-Jean Kim, Dinesh Patil, Mark Horowitz	Digital Circuit Optimization via Geometric Programming.	Operations Research	2005	DBLP DOI BibTeX RDF
1	Ghazi Al-Rawi, John M. Cioffi, Mark Horowitz	On task mapping optimization for parallel decoding of low-density parity-check codes on message-passing architectures.	Parallel Computing	2005	DBLP DOI BibTeX RDF
1	Ken Tseng, Mark Horowitz	False coupling exploration in timing analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin Cheung, Mark Horowitz, Stephen P. Boyd	A New Method for Design of Robust Digital Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
1	Marc Levoy, Billy Chen, Vaibhav Vaish, Mark Horowitz, Ian McDowall, Mark T. Bolas	Synthetic aperture confocal imaging.	ACM Trans. Graph.	2004	DBLP DOI BibTeX RDF	camera arrays, coded aperture, confocal microscopy, projector arrays, shaped illumination, Light fields, synthetic aperture
1	Francois Labonte, Peter R. Mattson, William Thies, Ian Buck, Christos Kozyrakis, Mark Horowitz	The Stream Virtual Machine.	IEEE PACT	2004	DBLP DOI BibTeX RDF
1	Bennett Wilburn, Neel Joshi, Vaibhav Vaish, Marc Levoy, Mark Horowitz	High-Speed Videography Using a Dense Camera Array.	CVPR	2004	DBLP DOI BibTeX RDF
1	David Lie, John C. Mitchell, Chandramohan A. Thekkath, Mark Horowitz	Specifying and Verifying Hardware for Tamper-Resistant Software.	IEEE Symposium on Security and Privacy	2003	DBLP DOI BibTeX RDF
1	David Lie, Chandramohan A. Thekkath, Mark Horowitz	Implementing an untrusted operating system on trusted hardware.	SOSP	2003	DBLP DOI BibTeX RDF	XOM, XOMOS, untrusted operating systems
1	Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang	Reshaping EDA for power.	DAC	2003	DBLP DOI BibTeX RDF
1	Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong	Design of a 10GHz clock distribution network using coupled standing-wave oscillators.	DAC	2003	DBLP DOI BibTeX RDF	distributed oscillators, on-chip phase measurement, resonant clocking, salphasic, standing wave, clock distribution, coupled oscillators
1	Isaac Keslassy, Shang-Tse Chuang, Kyoungsik Yu, David Miller, Mark Horowitz, Olav Solgaard, Nick McKeown	Scaling internet routers using optics.	SIGCOMM	2003	DBLP DOI BibTeX RDF	load-balancing, packet-switch, internet router
1	Dean Liu, Stefanos Sidiropoulos, Mark Horowitz	A Framework for Designing Reusable Analog Circuits.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Mark Horowitz	High-Speed Link Design, Then and Now. (PDF / PS)	ICCD	2003	DBLP DOI BibTeX RDF
1	Robert W. Brodersen, Mark Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic	Methods for true power minimization.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Jeff Solomon, Mark Horowitz	Using Texture Mapping with Mipmapping to Render a VLSI Layout.	DAC	2001	DBLP DOI BibTeX RDF
1	Ghazi Al-Rawi, John M. Cioffi, Mark Horowitz	Optimizing the Mapping of Low-Density Parity Check Codes on Parallel Decoding Architectures.	ITCC	2001	DBLP DOI BibTeX RDF
1	Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz	Smart Memories: a modular reconfigurable architecture.	ISCA	2000	DBLP DOI BibTeX RDF
1	Junji Ogawa, Mark Horowitz	A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro.	Intelligent Memory Systems	2000	DBLP DOI BibTeX RDF
1	David Lie, Chandramohan A. Thekkath, Mark Mitchell, Patrick Lincoln, Dan Boneh, John C. Mitchell, Mark Horowitz	Architectural Support for Copy and Tamper Resistant Software.	ASPLOS	2000	DBLP DOI BibTeX RDF
1	Rob A. Rutenbar, Cheming Hu, Mark Horowitz, Stephen Y. Chow	Life at the end of CMOS scaling (and beyond) (panel session) (abstract only).	DAC	2000	DBLP DOI BibTeX RDF
1	David L. Harris, Mark Horowitz, Dean Liu	Timing analysis including clock skew.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Jules P. Bergmann, Mark Horowitz	Vex - A CAD Toolbox.	DAC	1999	DBLP DOI BibTeX RDF
1	Hema Kapadia, Mark Horowitz	Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology.	DAC	1999	DBLP DOI BibTeX RDF
1	Ron Ho, Ken Mai, Hema Kapadia, Mark Horowitz	Interconnect scaling implications for CAD.	ICCAD	1999	DBLP BibTeX RDF
1	Jules P. Bergmann, Mark Horowitz	Improving coverage analysis and test generation for large designs.	ICCAD	1999	DBLP BibTeX RDF
1	Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith	Informing Memory Operations: Memory Performance Feedback Mechanisms and Their Applications.	ACM Trans. Comput. Syst.	1998	DBLP DOI BibTeX RDF	cache miss notification, processor architecture, memory latency
1	Nick McKeown, Martin Izzard, Adisak Mekkittikul, Bill Ellersick, Mark Horowitz	The Tiny Tera: A Packet Switch Core	CoRR	1998	DBLP BibTeX RDF
1	Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy	The Stanford FLASH Multiprocessor.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz	An Evaluation of Directory Schemes for Cache Coherence.	25 Years ISCA: Retrospectives and Reprints	1998	DBLP DOI BibTeX RDF
1	Shankar G. Govindaraju, David L. Dill, Alan J. Hu, Mark Horowitz	Approximate Reachability with BDDs Using Overlapping Projections.	DAC	1998	DBLP DOI BibTeX RDF	transceiver, spread spectrum communication, RF CMOS, digital radio, ISM frequency band
1	Dan Teodosiu, Joel Baxter, Kinshuk Govil, John Chapin, Mendel Rosenblum, Mark Horowitz	Hardware Fault Containment in Scalable Shared-Memory Multiprocessors.	ISCA	1997	DBLP DOI BibTeX RDF
1	David L. Harris, Stuart F. Oberman, Mark Horowitz	SRT Division Architectures and Implementations.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	skew-tolerant, Computer arithmetic, floating point units, SRT division, domino circuits
1	Mark Horowitz, Margaret Martonosi, Todd C. Mowry, Michael D. Smith	Informing Memory Operations: Providing Memory Performance Feedback in Modern Processors.	ISCA	1996	DBLP DOI BibTeX RDF
1	Gu-Yeon Wei, Mark Horowitz	A low power switching power supply for self-clocked systems.	ISLPED	1996	DBLP DOI BibTeX RDF
1	Mark Horowitz, Jan M. Rabaey, Brock Barton, Massoud Pedram (eds.)	Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996	ISLPED	1996	DBLP BibTeX RDF
1	Richard C. Ho, Mark Horowitz	Validation coverage analysis for complex digital designs.	ICCAD	1996	DBLP DOI BibTeX RDF	interactive behavioral synthesis, clock selection
1	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
1	Richard C. Ho, C. Han Yang, Mark Horowitz, David L. Dill	Architecture Validation for Processors.	ISCA	1995	DBLP DOI BibTeX RDF
1	Kimiyoshi Usami, Mark Horowitz	Clustered voltage scaling technique for low-power design.	ISLPD	1995	DBLP DOI BibTeX RDF
1	Russell Kao, Mark Horowitz	Timing analysis for piecewise linear Rsim.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
1	Russell Kao, Mark Horowitz	Eliminating redundant DC equations for asymptotic waveform evaluation.	IEEE Trans. on CAD of Integrated Circuits and Systems	1994	DBLP DOI BibTeX RDF
1	Mark E. Dean, David L. Dill, Mark Horowitz	Self-timed logic using Current-Sensing Completion Detection (CSCD).	VLSI Signal Processing	1994	DBLP DOI BibTeX RDF
1	James A. Gasbarro, Mark Horowitz	Techniques for Characterizing DRAMs With a 500-MHz Interface.	ITC	1994	DBLP DOI BibTeX RDF
1	Jeffrey Kuskin, David Ofelt, Mark Heinrich, John Heinlein, Richard Simoni, Kourosh Gharachorloo, John Chapin, David Nakahira, Joel Baxter, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy	The Stanford FLASH Multiprocessor.	ISCA	1994	DBLP DOI BibTeX RDF
1	Mark Heinrich, Jeffrey Kuskin, David Ofelt, John Heinlein, Joel Baxter, Jaswinder Pal Singh, Richard Simoni, Kourosh Gharachorloo, David Nakahira, Mark Horowitz, Anoop Gupta, Mendel Rosenblum, John L. Hennessy	The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor.	ASPLOS	1994	DBLP DOI BibTeX RDF
1	James Laudon, Anoop Gupta, Mark Horowitz	Interleaving: A Multithreading Technique Targeting Multiprocessors and Workstations.	ASPLOS	1994	DBLP DOI BibTeX RDF
1	Russell Kao, Mark Horowitz	Piecewise linear models for Rsim.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Daniel Lenoski, James Laudon, Kourosh Gharachorloo, Wolf-Dietrich Weber, Anoop Gupta, John L. Hennessy, Mark Horowitz, Monica S. Lam	The Stanford Dash Multiprocessor.	IEEE Computer	1992	DBLP DOI BibTeX RDF
1	Michael D. Smith, Mark Horowitz, Monica S. Lam	Efficient Superscalar Performance Through Boosting.	ASPLOS	1992	DBLP DOI BibTeX RDF
1	Richard Simoni, Mark Horowitz	Modeling the Performance of Limited Pointers Directories for Cache Coherence.	ISCA	1991	DBLP DOI BibTeX RDF
1	Mark E. Dean, David L. Dill, Mark Horowitz	Self-Timed Logic Using Current-Sensing Completion Detection (CSCD).	ICCD	1991	DBLP BibTeX RDF
1	Don Stark, Mark Horowitz	Techniques for calculating currents and voltages in VLSI power supply networks.	IEEE Trans. on CAD of Integrated Circuits and Systems	1990	DBLP DOI BibTeX RDF
1	Michael D. Smith, Monica S. Lam, Mark Horowitz	Boosting Beyond Static Scheduling in a Superscalar Processor.	ISCA	1990	DBLP DOI BibTeX RDF
1	Anant Agarwal, Mark Horowitz, John L. Hennessy	An Analytical Cache Model.	ACM Trans. Comput. Syst.	1989	DBLP DOI BibTeX RDF
1	Steven A. Przybylski, Mark Horowitz, John L. Hennessy	Characteristics of Performance-Optimal Multi-Level Cache Hierarchies.	ISCA	1989	DBLP DOI BibTeX RDF
1	Michael D. Smith, Mike Johnson, Mark Horowitz	Limits on Multiple Instruction Issue.	ASPLOS	1989	DBLP DOI BibTeX RDF
1	A. Salz, Mark Horowitz	IRSIM: An Incremental MOS Switch-Level Simulator.	DAC	1989	DBLP DOI BibTeX RDF
1	Anant Agarwal, John L. Hennessy, Mark Horowitz	Cache Performance of Operating System and Multiprogramming Workloads.	ACM Trans. Comput. Syst.	1988	DBLP DOI BibTeX RDF
1	Steven A. Przybylski, Mark Horowitz, John L. Hennessy	Performance Tradeoffs in Cache Design.	ISCA	1988	DBLP BibTeX RDF
1	Anant Agarwal, Richard Simoni, John L. Hennessy, Mark Horowitz	An Evaluation of Directory Schemes for Cache Coherence.	ISCA	1988	DBLP BibTeX RDF
1	Don Stark, Mark Horowitz	Analyzing CMOS Power Supply Networks Using Ariel.	DAC	1988	DBLP BibTeX RDF

Publications of "Mark Horowitz" ( http://dblp.L3S.de/Authors/Mark_Horowitz )