| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Brad D. Bingham, Mark R. Greenstreet |
Modeling Energy-Time Trade-Offs in VLSI Computation.  |
IEEE Trans. Computers  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Suwen Yang, Ian W. Jones, Mark R. Greenstreet |
Synchronizer Performance in Deep Sub-Micron Technology.  |
ASYNC  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vijay Anand Korthikanti, Gul Agha, Mark R. Greenstreet |
On the Energy Complexity of Parallel Algorithms.  |
ICPP  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Suwen Yang, Robert J. Drost, Mark R. Greenstreet, Shahriar Mirabbasi, Frank O'Mahony |
Varactor-based signal restoration for near-speed-of-light surfing global interconnect.  |
CICC  |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Yan, Mark R. Greenstreet, Jochen Eisinger |
Formal Verification of an Arbiter Circuit.  |
ASYNC  |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Tarik Ono-Tesfaye, Mark R. Greenstreet |
A modular synchronizing FIFO for NoCs.  |
NOCS  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect.  |
NOCS  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark R. Greenstreet |
Verifying VLSI Circuits.  |
ATVA  |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet |
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.  |
FPGA  |
2009 |
DBLP DOI BibTeX RDF |
on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing |
| 1 | Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton |
Practical Asynchronous Interconnect Network Design.  |
IEEE Trans. VLSI Syst.  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Yan, Mark R. Greenstreet |
Verifying an Arbiter Circuit.  |
FMCAD  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark R. Greenstreet, Suwen Yang |
Verifying start-up conditions for a ring oscillator.  |
ACM Great Lakes Symposium on VLSI  |
2008 |
DBLP DOI BibTeX RDF |
formal verification, dynamical systems, oscillators |
| 1 | Brad D. Bingham, Mark R. Greenstreet |
Computation with Energy-Time Trade-Offs: Models, Algorithms and Lower-Bounds.  |
ISPA  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Brad D. Bingham, Mark R. Greenstreet |
Energy Optimal Scheduling on Multiprocessors with Migration.  |
ISPA  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao Yan, Mark R. Greenstreet |
Faster projection based methods for circuit level verification.  |
ASP-DAC  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Paul Teehan, Mark R. Greenstreet, Guy G. Lemieux |
A Survey and Taxonomy of GALS Design Styles.  |
IEEE Design & Test of Computers  |
2007 |
DBLP DOI BibTeX RDF |
globally asynchronous, locally synchronous (GALS), clock domains, pausible clocks, loosely synchronous, synchronization, asynchronous |
| 1 | Chao Yan, Mark R. Greenstreet |
Circuit Level Verification of a High-Speed Toggle.  |
FMCAD  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Suwen Yang, Mark R. Greenstreet, Jihong Ren |
A Jitter Attenuating Timing Chain.  |
ASYNC  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Suwen Yang, Mark R. Greenstreet |
Simulating Improbable Events.  |
DAC  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Suwen Yang, Mark R. Greenstreet |
Computing synchronizer failure probabilities.  |
DATE  |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Suwen Yang, Mark R. Greenstreet |
Analysing the Robustness of Surfing Circuits.  |
Electr. Notes Theor. Comput. Sci.  |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark R. Greenstreet, Jihong Ren |
Surfing Interconnect.  |
ASYNC  |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Suwen Yang, Brian D. Winters, Mark R. Greenstreet |
Energy Efficient Surfing.  |
ASYNC  |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jihong Ren, Mark R. Greenstreet |
A unified optimization framework for equalization filter synthesis.  |
DAC  |
2005 |
DBLP DOI BibTeX RDF |
equalizing filters, optimal synthesis, linear programming, crosstalk |
| 1 | Suwen Yang, Mark R. Greenstreet |
Noise margin analysis for dynamic logic circuits.  |
ICCAD  |
2005 |
DBLP BibTeX RDF |
|
| 1 | Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton |
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow.  |
ICCD  |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jihong Ren, Mark R. Greenstreet |
Crosstalk Cancellation for Realistic PCB Buses.  |
PATMOS  |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Jihong Ren, Mark R. Greenstreet |
A Signal Integrity Test Bed for PCB Buses.  |
ICCD  |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Brian D. Winters, Mark R. Greenstreet |
Surfing: a robust form of wave pipelining using self-timed circuit techniques.  |
Microprocessors and Microsystems  |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jihong Ren, Mark R. Greenstreet |
Equalizing Filter Design for Crosstalk Cancellation.  |
ISVLSI  |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ajanta Chakraborty, Mark R. Greenstreet |
Efficient Self-Timed Interfaces for Crossing Clock Domains.  |
ASYNC  |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Jihong Ren, Mark R. Greenstreet |
Synthesizing optimal filters for crosstalk-cancellation for high-speed buses.  |
DAC  |
2003 |
DBLP DOI BibTeX RDF |
equalizing filters, optimal synthesis, crosstalk, buses |
| 1 | Mark R. Greenstreet, Anthony Winstanley, Aurélien Garivier |
An Event Spacing Experiment.  |
ASYNC  |
2002 |
DBLP DOI BibTeX RDF |
Charlie Diagrams, self-timed rings, timing analysis, phase transitions, attractors, hysteresis |
| 1 | Mark R. Greenstreet, Brian D. Winters |
A Negative-Overhead, Self-Timed Pipeline.  |
ASYNC  |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Claire Tomlin, Mark R. Greenstreet (eds.) |
Hybrid Systems: Computation and Control, 5th International Workshop, HSCC 2002, Stanford, CA, USA, March 25-27, 2002, Proceedings  |
HSCC  |
2002 |
DBLP BibTeX RDF |
|
| 1 | Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet |
A light-weight framework for hardware verification.  |
STTT  |
2001 |
DBLP DOI BibTeX RDF |
Refinement, Theorem-proving, Timing verification, Switch-level models, SRT division |
| 1 | Mark R. Greenstreet, Brian de Alwis |
How to Achieve Worst-Case Performance.  |
ASYNC  |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Anthony Winstanley, Mark R. Greenstreet |
Temporal Properties of Self-Timed Rings.  |
CHARME  |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Christoph Kern, Mark R. Greenstreet |
Formal verification in hardware design: a survey.  |
ACM Trans. Design Autom. Electr. Syst.  |
1999 |
DBLP DOI BibTeX RDF |
language containment, model checking, formal methods, formal verification, case studies, theorem proving, survey, hardware verification |
| 1 | Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet |
A Light-Weight Framework for Hardware Verification.  |
TACAS  |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark R. Greenstreet |
Real-Time Merging.  |
ASYNC  |
1999 |
DBLP DOI BibTeX RDF |
bounded-time, receptive mixer, real-time, merging, arbitration, metastability |
| 1 | Mark R. Greenstreet, Tarik Ono-Tesfaye |
A Fast, asP*, RGD Arbiter. (PDF / PS)  |
ASYNC  |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark R. Greenstreet, Ian Mitchell |
Reachability Analysis Using Polygonal Projections.  |
HSCC  |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Tarik Ono-Tesfaye, Christoph Kern, Mark R. Greenstreet |
Verifying a Self-Timed Divider.  |
ASYNC  |
1998 |
DBLP DOI BibTeX RDF |
model checking, refinement, asynchronous, hardware verification, timing verification, self-timed, speed-independence |
| 1 | Mark R. Greenstreet, Ian Mitchell |
Integrating Projections.  |
HSCC  |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Peggy B. K. Pang, Mark R. Greenstreet |
Self-Timed Meshes Are Faster Than Synchronous.  |
ASYNC  |
1997 |
DBLP DOI BibTeX RDF |
self-timed meshes, linear speed-up, per-processor performance, simulation, logic CAD |
| 1 | Mark R. Greenstreet |
Verifying Safety Properties of Differential Equations.  |
CAV  |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger |
Automatic Verification of Asynchronous Circuits.  |
IEEE Design & Test of Computers  |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Mark R. Greenstreet |
Implementing a STARI chip. (PDF / PS)  |
ICCD  |
1995 |
DBLP DOI BibTeX RDF |
STARI chip, high-speed signaling technique, MOSIS 2/spl mu/ CMOS process, self-timed FIFO, robust compensation, clock skew, digital signal processing chips, CMOS digital integrated circuits, self-timed circuits, synchronous circuits, 2 micron, timing circuits |
| 1 | Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger |
Automatic Verification of Refinement.  |
ICCD  |
1994 |
DBLP BibTeX RDF |
|
| 1 | Mark R. Greenstreet |
Using Synchronized Transitions for Simulation and Timing Verification.  |
Designing Correct Circuits  |
1992 |
DBLP BibTeX RDF |
|
| 1 | Mark R. Greenstreet, Kenneth Steiglitz |
Bubbles can make self-timed pipelines fast.  |
VLSI Signal Processing  |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Jørgen Staunstrup, Mark R. Greenstreet |
From High-Level Descriptions to VLSI Circuits.  |
BIT  |
1988 |
DBLP BibTeX RDF |
|