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Publications of "Markus Bühler" ( http://dblp.L3S.de/Authors/Markus_Bühler )

  Author page on DBLP  Author page in RDF  Community of Markus Bühler in ASPL-2

Publication years (Num. hits)
1999 (1) 2006 (2) 2008 (1) 2009 (1) 2011 (2)
Publication types (Num. hits)
inproceedings(7)
Venues (Conferences, Journals, ...)
DATE(2) SoCC(2) ACM Great Lakes Symposium on V...(1) ICCAD(1) ISQED(1)
Authors
Markus Bühler(7) Erich Barke(4) Markus Olbrich(4) Jürgen Koehl(3) Lei Wang(3) Philipp V. Panitz(3) Thomas Büchner(3) Jason Hibbeler(2) Jeanne Bickford(2) Andreas Ripp(1) Christian Schulte 0002(1) Dirk Muller(1) K. Kapp(1) Matthias Papesch(1) Michael Pronath(1) R. Sommer(1) More (+10 of total 19)
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Found 7 publication records. Showing 7 according to the selection in the facets
Hits ?▲ Authors Title Venue Year Link Author keywords
1Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz A gate sizing method for glitch power reduction. Search on Bibsonomy SoCC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz A theoretical probabilistic simulation framework for dynamic power estimation. Search on Bibsonomy ICCAD The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
1Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler Fast dynamic power estimation considering glitch filtering. Search on Bibsonomy SoCC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl Considering possible opens in non-tree topology wire delay calculation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF non-tree topologies, yield, static timing analysis, delay analysis
1Jeanne Bickford, Jason Hibbeler, Markus Bühler, Jürgen Koehl, Dirk Muller, Sven Peyer, Christian Schulte 0002 Yield Improvement by Local Wiring Redundancy. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Markus Bühler, Jürgen Koehl, Jeanne Bickford, Jason Hibbeler, Ulf Schlichtmann, R. Sommer, Michael Pronath, Andreas Ripp DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
1Markus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
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