|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 3 occurrences of 3 keywords
|
|
|
|
|
Results
Found 6 publication records. Showing 6 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Martin Saint-Laurent, Animesh Datta |
A low-power clock gating cell optimized for low-voltage operation in a 45-nm technology.  |
ISLPED  |
2010 |
DBLP DOI BibTeX RDF |
clock gater, clock gating cell, local clock buffer, set-reset latch |
| 1 | Baker Mohammad, Martin Saint-Laurent, Paul Bassett, Jacob A. Abraham |
Cache Design for Low Power and High Yield. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
reduce voltage swing, sram yield, SRAM 6T cell, cache design, parametric failure |
| 1 | Martin Saint-Laurent |
A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Martin Saint-Laurent, Baker Mohammad, Paul Bassett |
A 65-nm pulsed latch with a single clocked transistor. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
low voltage swing, minimum clock power, pulsed latch, virtual-ground clocking |
| 1 | Martin Saint-Laurent, Vojin G. Oklobdzija, Simon S. Singh, Madhavan Swaminathan |
Optimal Sequencing Energy Allocation for CMOS Integrated Systems. (PDF / PS) |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
Energy Allocation, Clocked Storage Elements, Clock Distribution |
| 1 | Martin Saint-Laurent, Madhavan Swaminathan, James D. Meindl |
On The Micro-architectural Impact of Clock Distribution Using Multiple PLLs. |
ICCD |
2001 |
DBLP BibTeX RDF |
|
Displaying result #1 - #6 of 6 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")