Search results for "Martti Forsell"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Martti Forsell	Performance comparison of some shared memory organizations for 2D mesh-like NOCs.	Microprocessors and Microsystems - Embedded Hardware Design	2011	DBLP DOI BibTeX RDF
1	Martti Forsell	A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads.	IJNC	2011	DBLP BibTeX RDF
1	Martti Forsell, Ville Leppänen	A moving threads processor architecture MTPA.	The Journal of Supercomputing	2011	DBLP DOI BibTeX RDF
1	Ville Leppänen, Martti Penttonen, Martti Forsell	A layout for sparse cube-connected-cycles network.	CompSysTech	2011	DBLP DOI BibTeX RDF
1	Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell	RISC-based moving threads multicore architecture.	CompSysTech	2011	DBLP DOI BibTeX RDF
1	Martti Forsell, Ville Leppänen, Martti Penttonen	Cost of Sparse Mesh Layouts Supporting Throughput Computing.	DSD	2011	DBLP DOI BibTeX RDF
1	Martti Forsell	On the Performance and Cost of Some PRAM Models on CMP Hardware.	Int. J. Found. Comput. Sci.	2010	DBLP DOI BibTeX RDF
1	Hai-Xiang Lin, Michael Alexander, Martti Forsell, Andreas Knüpfer, Radu Prodan, Leonel Sousa, Achim Streit (eds.)	Euro-Par 2009 - Parallel Processing Workshops, HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25-28, 2009, Revised Selected Papers	Euro-Par Workshops	2010	DBLP DOI BibTeX RDF
1	Martti Forsell, Jesper Larsson Träff	HPPC 2010: 5th Workshop on Highly Parallel Processing on a Chip.	Euro-Par Workshops	2010	DBLP DOI BibTeX RDF
1	Martti Forsell, Jesper Larsson Träff	HPPC 2010: Forth Workshop on Highly Parallel Processing on a Chip.	Euro-Par Workshops	2010	DBLP DOI BibTeX RDF
1	Martti Forsell	A PRAM-NUMA model of computation for addressing low-TLP workloads.	IPDPS Workshops	2010	DBLP DOI BibTeX RDF
1	Martti Forsell, Ville Leppänen	Supporting Concurrent Memory Access and Multioperations in Moving Threads CMPs.	PDPTA	2010	DBLP BibTeX RDF
1	Ville Leppänen, Martti Penttonen, Martti Forsell	Layouts for Sparse Networks Supporting Throughput Computing.	PDPTA	2010	DBLP BibTeX RDF
1	Martti Forsell, Jesper Larsson Träff	HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip.	Euro-Par Workshops	2009	DBLP DOI BibTeX RDF
1	Martti Forsell, Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff	HPPC 2009 Panel: Are Many-Core Computer Vendors on Track?	Euro-Par Workshops	2009	DBLP DOI BibTeX RDF
1	Jani Paakkulainen, Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell	Outline of RISC-based core for multiprocessor on chip architecture supporting moving threads.	CompSysTech	2009	DBLP DOI BibTeX RDF
1	Martti Forsell	Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions.	NOCS	2009	DBLP DOI BibTeX RDF
1	Martti Forsell, Ville Leppänen	MTPA - A Processor Architecture for MP-SOCs Employing the Moving Threads Paradigm.	PDPTA	2009	DBLP BibTeX RDF
1	Luc Bougé, Martti Forsell, Jesper Larsson Träff, Achim Streit, Wolfgang Ziegler, Michael Alexander, Stephen Childs (eds.)	Euro-Par 2007 Workshops: Parallel Processing, HPPC 2007, UNICORE Summit 2007, and VHPC 2007, Rennes, France, August 28-31, 2007, Revised Selected Papers	Euro-Par Workshops	2008	DBLP BibTeX RDF
1	Martti Forsell, Jesper Larsson Träff	Second Workshop on Highly Parallel Processing on a Chip (HPPC 2008).	Euro-Par Workshops	2008	DBLP DOI BibTeX RDF
1	Martti Forsell	On the performance and cost of some PRAM models on CMP hardware.	IPDPS	2008	DBLP DOI BibTeX RDF
1	Martti Forsell, Jussi Roivainen	Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architectures.	PDPTA	2008	DBLP BibTeX RDF
1	Martti Forsell, Jesper Larsson Träff	HPPC 2007: Workshop on Highly Parallel Processing on a Chip.	Euro-Par Workshops	2007	DBLP DOI BibTeX RDF
1	Martti Forsell, Ville Leppänen	Moving Threads: A Non-Conventional Approach for Mapping Computation to MP-SOC.	PDPTA	2007	DBLP BibTeX RDF
1	Martti Forsell	Realising constant time parallel algorithms with active memory modules.	IJEB	2005	DBLP DOI BibTeX RDF
1	Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar	Extending Platform-Based Design to Network on Chip Systems.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Eugene I. Ageenko, Martti Forsell, Pasi Fränti	Context-based compression of binary images in parallel.	Softw., Pract. Exper.	2002	DBLP DOI BibTeX RDF
1	Martti Forsell	A Scalable High-Performance Computing Solution for Networks on Chips.	IEEE Micro	2002	DBLP DOI BibTeX RDF
1	Martti Forsell	Architectural differences of efficient sequential and parallel computers.	Journal of Systems Architecture	2002	DBLP DOI BibTeX RDF
1	Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani	A Network on Chip Architecture and Design Methodology.	ISVLSI	2002	DBLP DOI BibTeX RDF	System on Chip, IP, Platform based design, On-chip communication
1	Juha-Pekka Soininen, Jari Kreku, Yang Qu, Martti Forsell	Fast processor core selection for WLAN modem using mappability estimation.	CODES	2002	DBLP DOI BibTeX RDF	mappability estimation, processor architecture evaluation, codesign, cost function
1	Martti Forsell	MTAC - A Multithreaded VLIW Architecture for PRAM Simulation.	J. UCS	1997	DBLP BibTeX RDF
1	Martti Forsell, Martti Penttonen, Ville Leppänen	Efficient Two-Level Mesh based Simulation of PRAMs.	ISPAN	1996	DBLP DOI BibTeX RDF	time-processor optimal, simulation, interconnection network, mesh, PRAM, shared memory machine

Publications of "Martti Forsell" ( http://dblp.L3S.de/Authors/Martti_Forsell )