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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 11 occurrences of 11 keywords
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Results
Found 29 publication records. Showing 29 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Nobuaki Ozaki, Yoshihiro Yasuda, Mai Izawa, Yoshiki Saito, Daisuke Ikebuchi, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo |
Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips.  |
IEEE Micro  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nobuaki Ozaki, Yoshihiro Yasuda, Yoshiki Saito, Daisuke Ikebuchi, Masayuki Kimura, Hideharu Amano, Hiroshi Nakamura, Kimiyoshi Usami, Mitaro Namiki, Masaaki Kondo |
Cool Mega-Array: A highly energy efficient reconfigurable accelerator. |
FPT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Zhao, Daisuke Ikebuchi, Yoshiki Saito, M. Kamata, Naomi Seki, Yu Kojima, Hideharu Amano, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, D. Masuda, Kimiyoshi Usami, Keiji Kimura, Mitaro Namiki, Seidai Takeda, Hiroshi Nakamura, Masaaki Kondo |
Geyser-2: The second prototype CPU with fine-grained run-time power gating. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Kimiyoshi Usami, Tatsunori Hashida, Satoshi Koyama, Tatsuya Yamamoto, Daisuke Ikebuchi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura |
Adaptive power gating for function units in a microprocessor. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo |
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura |
Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Noriko Takagi, Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura |
Cooperative shared resource access control for low-power chip multiprocessors. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
low power, chip multiprocessors, cache partitioning, dvfs, resource conflict |
| 1 | Kimiyoshi Usami, Toshiaki Shirai, Tatsunori Hashida, Hiroki Masuda, Seidai Takeda, Mitsutaka Nakata, Naomi Seki, Hideharu Amano, Mitaro Namiki, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura |
Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Hiroshi Sasaki, Takatsugu Oya, Masaaki Kondo, Hiroshi Nakamura |
Power-performance modeling of heterogeneous cluster-based web servers. |
GRID |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Naomi Seki, Lei Zhao, Jo Kei, Daisuke Ikebuchi, Yu Kojima, Yohei Hasegawa, Hideharu Amano, Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Mitsutaka Nakata, Kimiyoshi Usami, Tetsuya Sunata, Jun Kanai, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura |
A fine-grain dynamic sleep control scheme in MIPS R3000. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Masaaki Kondo, Hiroshi Sasaki, Hiroshi Nakamura |
Improving fairness, throughput and energy-efficiency on a chip multiprocessor through DVFS. |
SIGARCH Computer Architecture News |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Masaaki Kondo, Yoshimichi Ikeda, Hiroshi Nakamura |
A High Performance Cluster System Design by Adaptie Power Control. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura |
An intra-task dvfs technique based on statistical analysis of hardware events. |
Conf. Computing Frontiers |
2007 |
DBLP DOI BibTeX RDF |
statistical analysis, performance estimation, DVFS, hardware performance counters |
| 1 | Ryo Watanabe, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura, Takashi Nanya |
Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya |
Power reduction of chip multi-processors using shared resource control cooperating with DVFS. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kouichi Watanabe, Masashi Imai, Masaaki Kondo, Hiroshi Nakamura, Takashi Nanya |
Design Method of High Performance and Low Power Functional Units Considering Delay Variations. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura |
Energy-efficient dynamic instruction scheduling logic through instruction grouping. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
instruction grouping, issue queue, dynamic instruction scheduling |
| 1 | Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura |
Dynamic Instruction Cascading on GALS Microprocessors. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chikafumi Takahashi, Mitsuhisa Sato, Daisuke Takahashi, Taisuke Boku, Hiroshi Nakamura, Masaaki Kondo, Motonobu Fujita |
Empirical Study for Optimization of Power-Performance with On-Chip Memory. |
ISHPC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Masaaki Kondo, Hiroshi Nakamura |
A Small, Fast and Low-Power Register File by Bit-Partitioning. |
HPCA |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura |
Data Movement Optimization for Software-Controlled On-Chip Memory. |
Interaction between Compilers and Computer Architectures |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Hiroshi Nakamura, Takuro Hayashida, Masaaki Kondo, Yuya Tajima, Masashi Imai, Takashi Nanya |
Skewed Checkpointing for Tolerating Multi-Node Failures. |
SRDS |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Masaaki Kondo, Hiroshi Nakamura |
Dynamic Processor Throttling for Power Efficient Computations. |
PACS |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, Daisuke Takahashi, Hiroshi Nakamura, Mitsuhisa Sato |
SCIMA-SMP: on-chip memory processor architecture for SMP. |
WMPI |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Masaaki Kondo, Motonobu Fujita, Hiroshi Nakamura |
Software-controlled on-chip memory for high-performance and low-power computing. |
SIGARCH Computer Architecture News |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | T. Ohneda, Masaaki Kondo, Masashi Imai, Hiroshi Nakamura |
Design and evaluation of high performance microprocessor with reconfigurable on-chip memory. |
APCCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Masaaki Kondo, Mitsugu Iwamoto, Hiroshi Nakamura |
Cache Line Impact on 3D PDE Solvers. |
ISHPC |
2002 |
DBLP BibTeX RDF |
|
| 1 | Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku |
Software Controlled Reconfigurable On-Chip Memory for High Performance Computing. |
Intelligent Memory Systems |
2000 |
DBLP DOI BibTeX RDF |
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| 1 | Masaaki Kondo, Hideki Okawara, Hiroshi Nakamura, Taisuke Boku |
SCIMA: Software Controlled Integrated Memory Architecture for High Performance Computing. (PDF / PS) |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #29 of 29 (100 per page; Change: )
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