Search results for "Masaharu Imai"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A Small-Area and Low-Power SoC for Less-Invasive Pressure Sensing Capsules in Ambulatory Urodynamic Monitoring.	IEICE Transactions	2012	DBLP BibTeX RDF
1	Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Two-Stage Configurable Decoder Model for Domain Specific FEC Decoder Design.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Keishi Sakanushi, Takuji Hieda, Taichiro Shiraishi, Yasumasa Ode, Yoshinori Takeuchi, Masaharu Imai, Teruo Higashino, Hiroshi Tanaka	Electronic Triage System: Casualties Monitoring System in the Disaster Scene.	3PGCIC	2011	DBLP DOI BibTeX RDF
1	Masaharu Imai, Yoshinori Takeuchi, Keishi Sakanushi, Hirofumi Iwato	Biological information sensing technologies for medical, health care, and wellness applications.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto, Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai	A new compilation technique for SIMD code generation across basic block boundaries.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Hassan A. Youness, Abdel-Moniem Wahdan, Mohammed Hassan, Ashraf Salem, Mohammed Moness, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Efficient partitioning technique on multiple cores based on optimal scheduling and mapping algorithm.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Ittetsu Taniguchi, Ayataka Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Two-stage configurable decoder model for multiple forward error correction standards.	ESTImedia	2010	DBLP DOI BibTeX RDF
1	Takuji Hieda, Hiroaki Tanaka, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Heuristic Instruction Scheduling Algorithm Using Available Distance for Partial Forwarding Processor.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Ittetsu Taniguchi, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Yoshinori Takeuchi, Masaharu Imai	Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Hassan A. Youness, Keishi Sakanushi, Yoshinori Takeuchi, Ashraf Salem, Abdel-Moneim Wahdan, Masaharu Imai	Optimal Scheme for Search State Space and Scheduling on Multiprocessor Systems.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Ittetsu Taniguchi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Efficient Method to Generate an Energy Efficient Schedule Using Operation Shuffling.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Operation shuffling over cycle boundaries for low energy L0 clustering.	ASAP	2008	DBLP DOI BibTeX RDF
1	Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Hiroki Tagawa, Yutaka Ota, Nobu Matsumoto	Generation of Pack Instruction Sequence for Media Processors Using Multi-Valued Decision Diagram.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Compilers for low energy, loop buffers, VLIW processors
1	M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC	CoRR	2007	DBLP BibTeX RDF
1	Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A low power VLIW processor generation method by means of extracting non-redundant activation conditions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	low power, ASIP, clock gating, VLIW processor
1	Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa	Pack instruction generation for media pUsing multi-valued decision diagram.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multi-valued decision diagram, SIMD instructions
1	Masaharu Imai, Akira Kitajima	Verification Challenges in Configurable Processor Design with ASIP Meister.	CHARME	2005	DBLP DOI BibTeX RDF
1	M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Enabling RTOS simulation modeling in a system level design language.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Laurence Tianruo Yang, Hamid R. Arabnia, Jürgen Becker, Masaharu Imai, Zoran A. Salcic (eds.)	Proceedings of The 2005 International Conference on Embedded Systems and Applications, ESA 2005, Las Vegas, Nevada, USA, June 27-30, 2005	ESA	2005	DBLP BibTeX RDF
1	M. Abdelsalam Hassan, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	RTK-Spec TRON: A Simulation Model of an ITRON Based RTOS Kernel in SystemC.	DATE	2005	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai	Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.	ESTImedia	2005	DBLP DOI BibTeX RDF
1	H. M. AbdElSalam, Shinsuke Kobayashi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Towards a Higher Level of Abstraction in Hardware/Software Co-Simulation.	ICDCS Workshops	2004	DBLP DOI BibTeX RDF
1	Yuki Kobayashi, Shinsuke Kobayashi, Koji Okuda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Synthesizable HDL generation method for configurable VLIW processors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
1	Masaharu Imai (eds.)	Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004	ASP-DAC	2004	DBLP BibTeX RDF
1	Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	Architecture-Level Performance Estimation for IP-Based Embedded Systems.	DATE	2004	DBLP DOI BibTeX RDF
1	Yohei Ishimaru, Keishi Sakanushi, Shinsuke Kobayashi, Yoshinori Takeuchi, Masaharu Imai	S-sequence: a new floorplan representation method preserving room abutment relationships.	ISCAS	2004	DBLP BibTeX RDF
1	Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai	A Code Selection Method for SIMD Processors with PACK Instructions.	SCOPES	2003	DBLP DOI BibTeX RDF
1	Akira Kitajima, Toshiyuki Sasaki, Yoshinori Takeuchi, Masaharu Imai	Design of Application Specific CISC Using PEAS-III.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
1	Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai	Effectiveness of the ASIP design system PEAS-III in design of pipelined processors.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Hideki Yamauchi, Yoshinori Takeuchi, Masaharu Imai	VLSI Implementation of Fractal Image Compression Processor for Moving Pictures.	EUROMICRO	2001	DBLP DOI BibTeX RDF
1	Masaharu Imai, Gary Smith, Steven Schulz, Karen Bartleson, Daniel Gajski, Wolfgang Rosenstiel, Peter Flake, Hiroto Yasuura	One language or more?: how can we design an SoC at a system level?	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Makiko Itoh, Shigeaki Higaki, Yoshinori Takeuchi, Akira Kitajima, Masaharu Imai, Jun Sato, Akichika Shiomi	PEAS-III: An ASIP Design Environment. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Eiichirou Shigehara, Yoshinori Takeuchi, Masaharu Imai, Tsutomu Kimura	Application of FHM-Based Design Method to Scalable 2-D DCT Processor.	EUROMICRO	1999	DBLP DOI BibTeX RDF
1	Nguyen-Ngoc Bình, Masaharu Imai, Yoshinori Takeuchi	A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes.	ASP-DAC	1998	DBLP BibTeX RDF
1	Masaharu Imai, Eugenio Villar	ASPDAC 1995: HDL synthesizability and interoperability.	IEEE Design & Test of Computers	1996	DBLP BibTeX RDF
1	Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi	A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts.	DAC	1996	DBLP DOI BibTeX RDF
1	Binh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi	A hardware/software partitioning algorithm for pipelined instruction set processor.	EURO-DAC	1995	DBLP DOI BibTeX RDF
1	Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi	A hardware/software codesign method for pipelined instruction set processor using adaptive database.	ASP-DAC	1995	DBLP DOI BibTeX RDF
1	Masaharu Imai, Eugenio Villar	Future direction of synthesizability and interoperability of HDL's: part 1.	ASP-DAC	1995	DBLP DOI BibTeX RDF
1	Eugenio Villar, Masaharu Imai	Future direction of synthesizabilty and interoperability of HDL's: part 2.	ASP-DAC	1995	DBLP DOI BibTeX RDF
1	Alauddin Alomary, Takeharu Nakata, Yoshimichi Honma, Masaharu Imai, Nobuyuki Hikichi	An ASIP instruction set optimization algorithm with functional module sharing constraint.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Jun Sato, Masaharu Imai, Tetsuya Hakata, Alauddin Y. Alomary, Nobuyuki Hikichi	An Integrated Design Environment for Application Specific Integrated Processor.	ICCD	1991	DBLP BibTeX RDF
1	Hajime Miura, Masaharu Imai, Masafumi Yamashita, Toshihide Ibaraki	Implementation of Parallel Prolog on Tree Machines.	FJCC	1986	DBLP BibTeX RDF
1	Masaharu Imai, Yuuji Tateizumi, Yuuji Yoshida, Teruo Fukumura	The Architecture and Efficiency of DON: A Combinatorial Problem Oriented Multicomputer System.	ICDCS	1984	DBLP BibTeX RDF

Publications of "Masaharu Imai" ( http://dblp.L3S.de/Authors/Masaharu_Imai )